无法通过SPI闪存配置FPGA

我正在试用一块使用xc3s1200e的新 电路板。
在电路板中，我使用主SPI模式配置 FPGA，SPI器件是AT45DB642D。
我可以通过JTAG来确认FPGA。
我也可以通过“使用iMPACT直接编程”对SPI闪存进行编程。
但我无法通过SPI闪存配置FPGA。
我使用的配置模式是：
（M2，M1，M0）=（0,0,1）;（VS2，VS1，VS0）=（1,1,0）;
1.以下是我尝试从SPI启动FPGA后使用JTAG“读取状态寄存器”得到的结果。*** *** BATCH CMD：ReadStatusRegister -p 1此设备链的最大TCK工作频率：
10000.Valida ting chain ...边界扫描链成功验证。'1'：读取状态寄存器内容... CRC错误：0解密器安全设置：0DCM锁定：1DCI匹配：1legacy输入错误：GTS_CFG_B的0状态：GWE的0状态：
GHIGH的0状态：MODE引脚的0值M0：MODE引脚的1值M1：MODE引脚的0值M2：CFG_RDY的0值（INIT_B）：DONE引脚的1DONEIN输入：尝试写入FDRI时0IDCODE未验证：0write FDRI发出之前或之后
解密操作：0Decryptor键未按正确顺序使用：0
2.如果这个问题与FPGA的上电顺序和SPI闪存有关，我试着将PROG_B信号保持逻辑0一段时间，然后释放它。
但是sympton是一样的。
3.通过使用示波器，我可以看到CCLK信号，CSO_B是逻辑'0'。
但是我看不到从FPGA的MOSI引脚发出的启动命令以及SPI的回复。
当我监视MOSI引脚时，我重复按住PROG_B信号并释放它。
所以我认为我应该能够看到来自MOSI的命令，如果它运行良好的话。
4.在我的设计中，板上还有另一个32位微处理器，微处理器和FPGA之间有一些接口，canthese接口会导致问题吗？
提前帮助你。



以下为原文


I am dubugging a new board which uses xc3s1200e. In the board, I use master SPI mode to configure the FPGA, and the SPI device is AT45DB642D. I can confihure the FPGA through JTAG. Also I can program the SPI flash by "direct programming using iMPACT". But I cannot configure the FPGA through the SPI flash.
The configuration mode I use is:
(M2,M1,M0) = (0,0,1);
(VS2,VS1,VS0) = (1,1,0);

1.The following is what I got from "read the status register" using JTAG, after I tried to start the FPGA from the SPI.
// *** BATCH CMD : ReadStatusRegister -p 1
Maximum TCK operating frequency for this device chain: 10000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': Reading status register contents...
CRC error : 0
Decryptor security set : 0
DCM locked : 1
DCI matched : 1
legacy input error : 0
status of GTS_CFG_B : 0
status of GWE : 0
status of GHIGH : 0
value of MODE pin M0 : 1
value of MODE pin M1 : 0
value of MODE pin M2 : 0
value of CFG_RDY (INIT_B) : 1
DONEIN input from DONE pin : 0
IDCODE not validated while trying to write FDRI : 0
write FDRI issued before or after decrypt operation: 0
Decryptor keys not used in proper sequence : 0

2. In case that this problem related to the power up sequence of the FPGA and the SPI flash, I tried to hold the PROG_B signal to logic zero for sometime, then release it. But the sympton was the same.
3. By using the scope, I could see the CCLK signal, and the CSO_B was logic '0'. But I cannot see the startup commands sent out from the MOSI pin of FPGA and the reply from the SPI. While i was monitoring the MOSI pin, I repeatly hold PROG_B signal low and release it . So I think I should be able to see commands coming out from MOSI, if it works well.
4. In my design, there is another 32-bit microprocessor on the board, there are some interfaces between the microprocess and the FPGA, canthese interfaces cause the problem?
Thans in advance for your help.