CY7C68013A停止随机填充FIFO缓冲区

此外，EP2中断也停止触发。



以下为原文
Also, EP2 interrupt stops to trigger as well

下面是FPGA的波形图
每个读周期是每rdActuple 2个单词。主机总是发送多个4字节的数据包。
在IOLK的下降边缘采样，如果FLAGA不活跃（FIFONOT空，然后SLeeIS激活，然后在下一个IOLK下降边缘激活RDIS）。IOCKFRQ为6.25兆赫
屏幕截图29pNG
12.8 K



以下为原文
Here is the waveforms the FPGA generates
Each read cycle is 2 words per RD active. Host always sends packets which are multiple of 4 bytes.
FLAGA is sampled on falling edges of IOCLK, and if FLAGA is not active (FIFO not empty, then SLOE is activated, then RD is activated on next IOCLK falling edge. IOCLK freq is 6.25 MHz

• screenshot29.png12.8 K
  
  

你好，
请分享什么样的模式（自动/手动）FX2LP操作？请在这里粘贴代码。我想看一看。
当做，
加亚特里



以下为原文
Hi,

Please share things like in what mode (Auto/Manual) FX2LP is operating? Can you please paste your code here. I would like to take a look.

Regards,
Gayathri

这是初始化代码：
SycDelay-（）；IfCunFig＝0x03；/EXT时钟，从属FIFO SycDelayy（；EP1OutCFG＆AMP；= ~0x7f；SycDelay.）；EP1CIFG＆AMP；＝0x7f；SycDelay-（）；EP4CFG＆AMP；= ~0x7f；SycDelay-（）；Ep6CFG＆AMP；= ~0x7f；SycDelay-（）；EP8CFG＆AMP；= ~0x7f；SycDelayy（）；EP4FIFOFFG＝0；同步。RVCTL＝0x00；EP8FIFOFFG＝0；SycDelayle（）；Ep2FIFOFFG＝0x11；//Auto，WordFieldSycDelayle（）；PoFrAsAsAB＝0x08；//有效输出ISO 1024的DbBuf EP2CFG＝（1和lt；lt；7）*（0和lt；lt；6）（1和lt；4）（1和lt；3）（0 & lt；lt；0）；SycDelay.（Fixelt＝0x8）；删除（）；EP6FIFOFFG＝0；0；SycDelay-（）；FiPosie= 0x82.；SycDelay-（）；FiPosie= 0x00；SycDelay-（）；EP2BCL＝0x80；SycDelaye（）；EP2BCL＝0x80；SycDelaye（）；EP2BCL＝0x80；SycDelayy（）；EP2BCL＝0x80；//Debug引脚OEA= 0x03；
当主机选择接口时执行此代码：
FiPosit＝0x80；SycDelay-（）；FiPosie= 0x82.；SycDelay-（）；FixPoT＝0x00；SycDelay-（）；ToCTLL＝0x02；SycDelay-（）；ToCTL＝0x22；EP2BCL＝0x80；SycDelaye（）；EP2BCL＝0x80；SycDelaye（）；EP2BCL＝0x80；SycDelayy（）；EP2BCL＝0x80；



以下为原文
This is the initialization code:
REVCTL = 0x00;
SYNCDELAY();
IFCONFIG = 0x03; // ext. clock, slave FIFO
SYNCDELAY();
EP1OUTCFG &= ~0x7F;
SYNCDELAY();
EP1INCFG &= ~0x7F;
SYNCDELAY();
EP4CFG &= ~0x7F;
SYNCDELAY();
EP6CFG &= ~0x7F;
SYNCDELAY();
EP8CFG &= ~0x7F;
SYNCDELAY();
EP4FIFOCFG = 0;
SYNCDELAY();
EP6FIFOCFG = 0;
SYNCDELAY();
EP8FIFOCFG = 0;
SYNCDELAY();
EP2FIFOCFG = 0x11; // Auto, wordwide
SYNCDELAY();
PINFLAGSAB = 0x08;

// Valid Out ISO 1024 QuadBuf
EP2CFG = (1 << 7) | (0 << 6) | (1 << 4) | (1 << 3) | (0 << 0);
SYNCDELAY();
FIFORESET = 0x80;
SYNCDELAY();
FIFORESET = 0x82;
SYNCDELAY();
FIFORESET = 0x00;
SYNCDELAY();
EP2BCL = 0x80;
SYNCDELAY();
EP2BCL = 0x80;
SYNCDELAY();
EP2BCL = 0x80;
SYNCDELAY();
EP2BCL = 0x80;

//debug pin
OEA = 0x03;

And this code is executed when host selects interface:
FIFORESET = 0x80;
SYNCDELAY();
FIFORESET = 0x82;
SYNCDELAY();
FIFORESET = 0x00;
SYNCDELAY();

TOGCTL = 0x02;
SYNCDELAY();
TOGCTL = 0x22;

EP2BCL = 0x80;
SYNCDELAY();
EP2BCL = 0x80;
SYNCDELAY();
EP2BCL = 0x80;
SYNCDELAY();
EP2BCL = 0x80;

你好，
请尝试更换
FiPosie= 0x80；SycDelay-（）；FiPosie= 0x82.；SycDelay-（）；FiPosie= 0x00；SycDelay.（）；
具有
FiPosie= 0x80；SycDelay-（）；FiPosie= 0x02；SycDelay-（）；FiPosie= 0x00；SycDelay.（）；
当做，
加亚特里



以下为原文
Hi,

Please try replacing
FIFORESET = 0x80;
SYNCDELAY();
FIFORESET = 0x82;
SYNCDELAY();
FIFORESET = 0x00;
SYNCDELAY();
with
FIFORESET = 0x80;
SYNCDELAY();
FIFORESET = 0x02;
SYNCDELAY();
FIFORESET = 0x00;
SYNCDELAY();

Regards,
Gayathri

如果IDO如此，FLAGAis总是活跃的（FIFO空）



以下为原文
If I do so, FLAGA is always active (FIFO empty)

我注意到，当这个问题发生时，USBERRIRQ中的ISOP2比特被设置。



以下为原文
I have noticed that when this problem occurs, ISOEP2 bit in USBERRIRQ is set

你好，
请在www. CyPress网站上提供一个技术支持案例，这样工程师就可以看一看并帮助你走出去。
当做，
加亚特里



以下为原文
Hi,

Please cerate a tech support case at www.cypress.com, so that and one of engineers can take a look at it and help yo out.

regards,
Gayathri