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大家好，我想用PSOC3套件开发振动镜和信号发生器，希望用任何程序在我的笔记本上显示。我对PSoC有很深的了解。请各位论坛成员帮我设计这个项目。
以上来自于百度翻译 以下为原文 hello to everyone i want to develop oscillioscope and signal generator using psoc3 kit and want to display on my laptop using any program. i have very basic knowledge about psoc.Request to all forum member please help me to design this project 
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23个回答
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这里有一个PSoC 1 FFT应用说明，你可以从这个线程下载它。
HTTP://www. pSOCGooReR.COM/FUMRS/VIEW？PHP？F＝3和t＝5833 问候，Dana。 以上来自于百度翻译 以下为原文 There is a PSOC 1 FFT application note, you can download it from this thread - http://www.psocdeveloper.com/forums/viewtopic.php?f=3&t=5833 Regards, Dana. |
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@
看一下你的项目。做得好！这是这个论坛的瑰宝。 鲍勃 以上来自于百度翻译 以下为原文 @hli, had a look into your project. Well done!! that's a gem for this forum. Bob |
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沙金
实际上NEC在90年初有一个基于网络的DEV系统供客户使用。 EVE编译器的性能，以及显示。许多顾客 用于简单的片上显示控制器和数学测试用例。他们 SH3系列。 问候，Dana。 以上来自于百度翻译 以下为原文 @sachinbvp Actually NEC had a net based dev system in early 90's for customers to eval compiler perfromance, and display as well. A number of customers used it for simple test cases of on chip display controller and math. Their SH3 series. Regards, Dana. |
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好的，20位是好的，24位甚至更好。真的吗？？？？
在估计总误差时，精度大约为2%的ADC只需要8位的精度。这对示波器来说还不够吗？您可以将采样数据发送到UsBuTART以连接到您的笔记本电脑并显示信号。 我先从逻辑分析器开始，而不是使用范围。原因很明显，你可以并行地数字化8个通道，并在一个字节内编码所有逻辑状态。触发你的分析器相对容易。 当你通过PSoC侧和Windows端时，你得到了一个功能框架，你可以用它来实现一些模拟能力，比如模拟触发和最后的模拟测量。 这不是一个为期3天的周末项目，你必须投入一些想法。你选择什么语言（什么编译器）为Windows侧？ 但是当你从逻辑分析器开始编程的同时，记住你也要实现模拟信号，你会选择更灵活的数据结构。 我们在PSoC3论坛上，但是“速度的需要”让我思考如果选择PSOC5不是更好的，特别是因为SRAM有大量的芯片，并且有几个KB缓冲一些值使你的生活更容易。 开始小，思考大，代码灵活，世界是你的！ 鲍勃 以上来自于百度翻译 以下为原文 Well, 20 bits are good, 24 bits are even better.... Truly??? Having an accuracy of about 2 percent would only require 8 bits of precision for the ADC when estimating the overall errors. Wouldn't that be enough for an oscilloscope? You may send the sampled data to a USBUART to connect to your laptop and have the signals displayed there. I would start with a logic-analizer and not with a scope. The reasons are obvious, you can digitize 8 channels in parallel and code all logic states in a single byte. Triggering your analizer is relatively easy. When you are through with that, PSoC side and Windows side, you have got a functional framework which you can use to implement some analog capabilities as analog triggering and at last analog measuring. This is not a 3-days-at-weekend project, you'll have to put some thoughts in. What language (what compiler) are you choosing for the windows-side? But when you start with logic-analizer and while programming everything keeping in mind that you are going to implement analog signals as well you will choose your data-structure more flexible. We are here in PSoC3 forum, but the "Need for Speed" makes me thinking if it wouldn't be better to choose a PSoC5 especially because of the much larger amount of sram that comes with that chip and having a couple of KB to buffer some values makes (your) life easier. Start small, think big, code flexible and the world is yours! Bob |
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最终版本也有一个信号发生器组件（刚刚有一些硬件，我让它适合在那里：）。不幸的是，塞浦路斯没有把最后的参赛作品公诸于众，我也没有把它上传到任何地方。但我可以准备它，如果它有帮助的人。
以上来自于百度翻译 以下为原文 The final version version had also a signal generator component in it (there was just some hardware over and I made it fit in there :). Unfortunately Cypress didn't make the final entries to the contest public, and I have not uploaded it anywhere. But I can prepare it, if it helps somebody. |
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@ HLI
不确定你是否参考我的帖子，但是“等效时间采样”是采样。 & Nyquist 问候，Dana。 以上来自于百度翻译 以下为原文 @hli Not sure if you were refering to my post but "equivalent time sampling" is sampling << Nyquist. Regards, Dana. |
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现在针对信号发生器部分。阅读DAC和DMA。寻找WaveDAC8组件——它基本上提供了您需要的基本构建块。然后阅读DDS和NCOs，如果你想进一步改进你的解决方案。
你可能想看看HTTP://www. CyPress？RID＝50106和Cache＝0——在那里你可以找到一个基本的项目，可以满足你的需要。如果它在一个更先进的状态（尤其是更好的频率分辨率），但它现在还没有发布的状态。 以上来自于百度翻译 以下为原文 Now for the signal generator part. Read about the DAC and DMA. Look for the WaveDAC8 component - it basically gives you the basic building blocks you need. Then read about DDS and NCOs, if you want to refine your solution further. You may want to look at http://www.cypress.com/?rID=50106&cache=0 - there you find a basic project which may do what you need. If have it in a further advanced state (esp. better frequency resolution), but it is not in a state to publish it right now. |
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ETS正在取样。每触发一个样本，从一个触发器递增延迟到
下一步。以下是Teks的描述 顺序等效时间采样。顺序等效时间采样器每触发一个采样，独立于时间/DIV设置，或扫描速度，如图34所示。当检测到触发器时，在非常短但定义良好的延迟之后进行采样。当下一个触发器发生时，一个小的时间增量ΔT被加到这个延迟中，而数字化器需要另一个采样。这个过程被重复多次，在每次获取之前添加“ΔT”，直到填充时间窗口。采样点在示波器屏幕上显示时，沿着波形从左到右依次出现。 HTTP://ARI.UCSDEDU/NJMMABADI/类/通用/XYZ-SPECT.PDF 问候，Dana。 以上来自于百度翻译 以下为原文 ETS is under sampling. One sample per trigger, incrementally delayed from one trigger to the next. Here is Teks description - Sequential Equivalent-time Sampling. The sequential equivalent-time sampler acquires one sample per trigger, independent of the time/div setting, or sweep speed, as illustrated in Figure 34. When a trigger is detected, a sample is taken after a very short, but well-defined, delay. When the next trigger occurs, a small time increment – delta t – is added to this delay and the digitizer takes another sample. This process is repeated many times, with “delta t” added to each previous acquisition, until the time window is filled. Sample points appear from left to right in sequence along the waveform when displayed on the oscilloscope screen. http://aries.ucsd.edu/najmabadi/CLASS/COMMON/XYZ-Scope.pdf Regards, Dana. |
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一些想法
1）你的目标范围是什么？比如你需要奈奎斯特率吗？ 最有可能的是，你需要SAR，PSoC5，在BW中获得任何有意义的东西。PSOC3 DELSIG 显示的是你的奈奎斯特速率。所以你的模拟速率变成了1/2。你 当然可以使用等效时间采样，但是还有很多其他问题，比如 采样噪声等。 2）低频范围内最大的挑战之一是所有的代码基础使其可用。 Win.net想到了“肉，桂”部分的设计，除非你打算使用 显示连接到PSoC。然后你的MIP需要去处理它。 3）一种快速获取基本显示W/O几乎没有任何代码的方法是这样的， HTTP://www. SelMaSurvi.COM/STAMPPLOTT/DEXX.HTM 您可以使用多个COM方案，并将数据发送给它，并使用简单的脚本 将格式和情节。这将允许您获得一个模拟范围并运行。 迅速地。 4）如前所述，存储允许DSO测量并查找许多复杂的数据。 标准，像一个下降的脉冲，6个脉冲在一个行内的窗口，……PSoC 3种限制 在您可以提交多少RAM的情况下，必须生成一个堆栈的EVE性能。 及其要求。 只是有些想法，Dana。 以上来自于百度翻译 以下为原文 Some thoughts - 1) What is your target BW for the scope, eg. what Nyquist rate are you going to need ? Most likely you will need SAR, PSOC5, to get anything meaningful in BW. PSOC3 Delsig shows 384KPS which then = your Nyquist rate. So your analog rate, becomes 1/2 that. You of course can use equivalent time sampling, but then there is a ton of other issues, like sampling noise, etc.. 2) One of the biggest challenges in a low frequency scope is all the code base to make it usable. Win.net comes to mind for the "meat, GUI" portion of the design, unless you are going to use a display attached to PSOC. Then your MIP needs go way up handling that. 3) A fast way of getting a basic display w/o writing hardly any code is this freebe, http://www.selmaware.com/stampplot/index.htm You can use a number of com schemes and send the data to it and with simple scripts it will format and plot. This would allow you to get an analog scope up and running very quickly. 4) As previously mentioned, storage allows a DSO to measure and look for many complex criteria, like a dropped pulse, 6 pulses in a row inside a window,.........PSOC 3 kind of limited in how much RAM you can commit, an eval of stack performance would have to be made and its requirements. Just some thought, Dana. |
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001组件比其他组件更通用，它包含一个PSoC1、PSoC3和一个PSoC5可交换处理器模块。所以你不是固定在一个特殊的芯片上。
- 30已经获得了PSoC3，并且相对于高分辨率（最小噪声等）优化了ADC（而不是-001），但是这一块将不能满足HLI项目（PSOC 3上的SARS缺失）的要求。 -50与-30相同，包含PSoC5芯片。 因此，如果你不打算在下次开发PSoC1，那就使用一个-50板。 鲍勃 以上来自于百度翻译 以下为原文 The -001 Kit is more universal than the others, it contains a PSoC1, PSoC3 and a PSoC5 exchangeable processor module. So you are not fixed to a special chip. The -30 has got a PSoC3 and is (opposed to -001) optimized for ADC with high resolution (minimum noise etc.) but this board will not fulfill the requirements of hli's project (SARs are missing on PSoC 3) the -50 is the same as the -30 and contains a PSoC5 chip. So if you do not plan to develope for PSoC1 in the next time, take a -50 board. Bob |
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我的DDS的实现不是在Verilog，直到我学习Verilog我才有障碍。某物
我希望在接下来的几个月里完成。 所以我把它作为一个软件/ DMA驱动的解决方案使用IDAC（更快的设置时间）和PGA。对于 模拟部分。我用计数器计数完整的波形，通过时钟馈送到DMA，实现。 N突发能力。还计数器控制突发之间的延迟。给它一个普通的CAPA— 能力。波形表在运行时由简单的方程结果值填充，正弦，半正弦， 斜坡，三角形，正弦（x）/x… 数字脉冲发生器部分相似能力。 这只是项目的一小部分，很快就聚集在一起，大约几天。 不幸的是，PSOC家族工具中没有一个提供仿真。 DDS框图在这种情况下简单，它只是一个DAC放置在设计，表和DMA都做了 软件。 有一个WaveDAC组件由CyPress EE，HTTP://wwwyCysP.com／？RID＝54728 我在PSoC 1完成了一个几乎完成的设计，但使用外部模拟设备DDS部件，我需要 RF波形在60 MHz的区域，对于任何PSoC内部DDS解决方案来说，这是不可能的， Verilog或其他。 问候，Dana。 以上来自于百度翻译 以下为原文 My implementation of the DDS was not in Verilog, I am handicapped until I learn Verilog. Something I want to get done over next few months. So I did it as a software/DMA driven solution using IDAC (faster setlling time) and PGA. For the analog portion. I used counters to count complete waveforms, fed by clock to DMA, to implement the N burst capability. Also counters to control delay between bursts. To give it a general capa- bility. The Waveform table was filled at run time by simple equation result values, sine, half sine, ramp, triangle, sinc(x)/x....... The digital pulse generator portion similiar capabilities. This is only a small fractional part of project, came together quickly, a few days roughly. Unfortunately none of the PSOC family tools offer simulation in them. DDS block diagram in this case simple, its just a DAC placed on design, table and DMA all done in software. There is a wavedac component done by Cypress EE, http://www.cypress.com/?rID=54728 I have a design done in PSOC 1 almost finished, but uses external Analog Devices DDS parts, I need RF waveforms in the 60 Mhz area, and thats out of the question for any PSOC internal DDS solution, Verilog or otherwise. Regards, Dana. |
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如果您以前已经做过Verilog工作，您应该对PSoC数据路径组件感到有些熟悉。看看社区视频——有5个关于如何用数据路径开发自己的组件的讲座（WioCH大部分是在Verilog中完成的）。
至于NCO：PSoC SESESEI博客有一个NCO /累加器组件为您。与DMA和DAC组件一起使用它可以在大约5分钟内生成DDS: 对于你在链接博客中发现的DDS项目，我需要一个晚上（但我以前有一些PSoC体验）。AdVistor花了很多时间，因为涉及的东西太多了（例如，PC通信不是很好的文档），而狩猎的bug总是需要一些时间…… 以上来自于百度翻译 以下为原文 If you have done Verilog work before, you should feel somewhat at home with the PSoC data path components. Look at the community videos - there are 5 lectures about how to develop own components with the data path (whioch is done mostly in verilog). As for the NCO: the PSoC Sensei blog has a NCO/accumulator component for you. Using that together with an DMA and a DAC component gives you a DDS generator in about 5 minutes :) For the DDS project you found in the linked blog, I needed one evening (but I had some PSoC experience before). The admScope took much longer, beacuse there was so much more stuff involved (the PC communication for example was not so good documented), and hunting bugs always takes some time... |
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改善DAC的电压范围以及其速度的一种方法是使用PGA与它连接，只是将它作为输出缓冲器连接到VDAC。但无论如何，你需要一个外部放大器，你想跳过这个。
以上来自于百度翻译 以下为原文 One way to improve the voltage range of the DAC as well as its speed is to use a PGA with it - just connect it as output buffer to a VDAC. But since you will need an external amplifier anyways, you way want to skip that. |
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对于你的另一个问题：是的，这可以在A- 001上实现，因为这是PSoC5模块（我使用了-A 050工具包）。- 050应该具有更好的模拟性能，但由于我只使用了8位ADC，这就不重要了。您还需要改变外围引脚映射，也有其他端口可用。
对于硬件：没有额外的一个。只要你能在PSoC（输入电压、输出电压、输出电流）的范围内，就不需要别的。唯一的例外是一个图形LCD的独立模式的范围） 如果你看比赛页面，你也会发现一个柏树的视频，我看到了我的原型，你看到了那里的硬件。我只是在电路板上加了一个测试电路，以便显示范围。 以上来自于百度翻译 以下为原文 To your other question: yes, this can be implemented on a -001, since this as a PSoC5 module (I used a -050 kit though). The -050 should have the better analog performance, but since I used a 8bit-ADC only, this should not matter much. You will need to change the peripheral pin mapping also, there are other ports available. For the hardware: there is no additional one involved. As long as you can stay within the limits of the PSoC (input voltages, output voltages, output current), nothing else is needed. 8The only exception was a graphical LCD for the standalone mode of the scope) If you look at the contest pages, you also find a video of Cypress presenting my prototype, and you see the hardware there. I just added a test circuit to the board, to have something the scope can display :) |
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这是正确的，你必须要过采样才能得到Nyquist不保存的东西。
这是什么样的小波，一种新的（实际上是旧的）方法，将FRQ和振幅看作F（t）。 但等效时间采样可以非常接近Nyquist，但仅用于周期性。 波形。 问候，Dana。 以上来自于百度翻译 以下为原文 Thats correct, you have to oversample to get what Nyquist does not preserve, scale. Thats what Wavelets are for, a new (actually old) way of looking at freq and amplitude as a f(t). But equivalent time sampling can occur very close to Nyquist, but only for periodic waveforms. Regards, Dana. |
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ScChnbvp：只需接受我的项目，然后在DDS上删除一个示意页面。然后，编译项目，查找错误，删除所有引用的但不存在的内容。这里最复杂的部分是LCD的UI。
这里有一个旧版本的项目：HTTP://www. CyPress？COM/？ID＝3312和；CONID＝235，不包含DDS。相反，它包含了一些错误： 对于-001，只需改变LCD的端口，因为它在另一个端口上。其他一切都应该保持不变。检查晶体频率（取决于哪一个安装在您的板上）。 以上来自于百度翻译 以下为原文 @sachinbvp: just take my project, and remove the one schematic page with the DDS on it. After that, compile the project, look for errors come up and remove everything which is referenced but not there. The most complex part here will be the UI for the LCD. There is an old version of the project available here: http://www.cypress.com/?id=3312&conID=235 , which doesn't contain the DDS. But instead it contains some bugs :( For the -001, just change the ports for the LCD, since it is on another port there. Everything else should stay the same. Check for the crystal frequency (depending which one is installed on your board). |
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想知道如何用PSoC做小波变换。实际上，希望能有更多的来自柏树的DSP应用笔记。不确定是否有人用PSCO尝试FFT？
以上来自于百度翻译 以下为原文 Would like to know how to do wavelet transform with PSOC. Actually would love to have more DSP application notes from Cypress. Not sure if any one tried FFT with PSCO? |
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如果你想提高采样等效时间采样的有效BW
在许多范围内使用。注意你的模拟频道仍然必须有你的目标BW， 这就减轻了取样器所需的BW。 HTTP://www. TEK.COM/APPLICATION - NOTEN/WORT时间-等时采样 问候，Dana。 以上来自于百度翻译 以下为原文 If you want to boost the effective BW of your sampler equivalent time sampling is used in many scopes. Note your analog channel still must have your target BW, this just relieves the BW required by the sampler. http://www.tek.com/application-note/real-time-versus-equivalent-time-sampling Regards, Dana. |
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有趣的是，谷歌刚刚给了我最近比赛的链接：HTTP://www. CyPress？APP =论坛和ID；ID＝167和；RID＝66880（论坛已经消失，并且出于某种原因，这个帖子被整理成USB控制器论坛：）你在那里找到我的视频，以及最新的项目。
以上来自于百度翻译 以下为原文 Funny - Google just gave me the link to my entry for the recent contest: http://www.cypress.com/?app=forum&id=167&rID=66880 (the forum has disappeared, and for some reason this posting is sorted into the USB controllers forum :) There you find my video, and the most recent project. |
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