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嗨，
我用基于ARM的微控制器和XC3S200创建了一块电路板。 FPGA在Slave Parallel模式下编程，配置过程（使用.bit文件）似乎没问题：在INIT_B上没有发出错误信号，DONE在整个.bit文件（用ISE 8.2i创建）发送之前高达5个字节 到FPGA，FPGA输出引脚停止驱动为高电平。 问题是输入时钟信号（频率40 MHz）可以通过简单的逻辑门（仅用于测试）从时钟输入（GCLK引脚之一）传递到任何输出引脚（我可以在示波器上观察到）， 但不驱动任何连接（时钟输入）触发器。 所有触发器看起来都像是永久复位（清除）。 我有一个带有JTAG编程的XC3S200的测试板，它在几乎相同的配置中没有出现这样的问题。 主要区别在于外部时钟连接到普通I / O引脚之一，而不是GLCK引脚。 这可能是配置编程的问题吗？ 我应该做什么不同于JTAG编程，让Slave Parallel配置文件好吗？ 或者因为使用GLCK引脚作为外部时钟输入而出现问题？ 在此先感谢您的任何建议。 马尔钦 以上来自于谷歌翻译 以下为原文 Hi, I have created a board with an ARM-based microcontroller and XC3S200. FPGA is programmed in Slave Parallel mode, and the configuration process (using .bit file) seems to go fine: no error is signalled on INIT_B, DONE goes high 5 bytes before the entire .bit file (created with ISE 8.2i) is sent to the FPGA, and the FPGA output pins stop driving high. The problem is that the input clock signal (frequency 40 MHz) can be passed from a clock input (one of GCLK pins) to any output pin (I can observe this on an oscilloscope) via simple logical gates (made for tests only), but does not drive any connected (clock input) flip-flops. All flip-flops look like permanently reset (cleared). I have a test board with XC3S200 programmed by JTAG which did not exhibit such a problem in a virtually identical configuration; the main difference is that the external clock was connected to one of ordinary I/O pins, not to GLCK one. Can it be a problem with configuration programming? What should I do differently than for JTAG programming, to get Slave Parallel configuration file ok? Or there is a problem because of using a GLCK pin as the external clock input? Thanks in advance for any suggestions. Marcin 
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4个回答
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问题可能是由于DONE变高后没有发送少量剩余字节引起的。
我们假设在DONE之后不需要它们，并且只是让CCLK长时间运行; 有效地将最后一个字节重新发送了几次。 现在它有效。 谢谢！ 马尔钦 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 The problem might have been caused by not sending the few remaining bytes after DONE went high. We have assumed that they are not needed after DONE and just kept CCLK running long after; effectively the last byte has been resent a few times. Now it works. Thanks! Marcin View solution in original post |
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确保在bitgen选项中将启动时钟配置为CCLK。
然后确保继续驱动CCLK循环次数 在DONE变高后，您的启动设置需要。 你可以改变 启动设置，以便尽快释放FPGA从内部复位 比更改CCLK驱动软件更容易。 通常是启动顺序 DONE变高后需要几个时钟。 这是必需的 多个FPGA需要一起出现。 有一个单独的FPGA 在释放内部复位之前，没有必要等待DONE。 HTH， 的Gabor - Gabor 以上来自于谷歌翻译 以下为原文 Make sure that the startup clock is configured to be CCLK in the bitgen options. Then make sure that you continue to drive CCLK for the number of cycles required by your startup settings after DONE goes high. You can change the startup settings to release the FPGA from internal reset sooner if that is easier than changing the CCLK driving software. Usually the startup sequence requires several clocks after DONE goes high. This is required when you have multiple FPGA's that need to come up together. FOr a single FPGA there is no real need to wait for DONE before releasing the internal reset. HTH, Gabor -- Gabor |
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问题可能是由于DONE变高后没有发送少量剩余字节引起的。
我们假设在DONE之后不需要它们，并且只是让CCLK长时间运行; 有效地将最后一个字节重新发送了几次。 现在它有效。 谢谢！ 马尔钦 以上来自于谷歌翻译 以下为原文 The problem might have been caused by not sending the few remaining bytes after DONE went high. We have assumed that they are not needed after DONE and just kept CCLK running long after; effectively the last byte has been resent a few times. Now it works. Thanks! Marcin |
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我认为你必须发送到FPGA * .BIN文件而不是* .BIT文件，对于XC3S400的Slave Parallel配置我只使用* .BIN文件。
拉德克 以上来自于谷歌翻译 以下为原文 I think that you must send to FPGA *.BIN file and not *.BIT file, For Slave Parallel configuration of XC3S400 I use *.BIN file only. Radek |
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