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我一直在使用ti TMS320c6713 DSP处理器开发DSP应用程序，但我想看看与这个处理器或任何其他专用浮点处理器相比，FPGA的性能如何。
最近我很高兴地看到FPGA已经准备好用于许多浮点应用的处理器，我想知道Spartan3an是否可以配置为提供与专用浮动速度相当或接近的高速浮点处理 点处理器。 如果不是Spartan3，那么FPGA芯片将完成任务。 此外，达到这种浮点速度需要什么IP。 谢谢你的时间， 裂 以上来自于谷歌翻译 以下为原文 I have been developing a DSP application using the TI TMS320c6713 DSP processor, but i would like to see how an FPGA will perform compared to this processor, or any other dedicated floating point processors. I am quite excited to read recently that FPGAs are poised to eclipse processors for many floating point applications, and i'm wondering if the Spartan3an can be configured to provide high speed floating point processing on par with or close to the speeds of a dedicated floating point processor. If not the Spartan3, then what FPGA chip would be up to the task. Also, what IP would be required to reach such floating point speeds. Thanks for your time, Bobr 
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这是家庭作业还是商业开发项目？
最近我很高兴地看到FPGA已经准备好为很多浮点应用程序的处理器。 FPGA上的浮点运算是一个复杂的设计问题，一个复杂的设计验证问题，以及一个资源匮乏（昂贵）的实现。 总体而言，需要浮点运算的应用程序也受益于全开处理器提供的其他功能。 - 鲍勃埃尔金德 签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。 阅读手册或用户指南。 你读过手册了吗？ 你能找到手册吗？2。 搜索论坛（并搜索网页）以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题，开始新的主题！5。 学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息（请与网页，数据表链接）.7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章，那么我一无所获。 以上来自于谷歌翻译 以下为原文 Is this a homework assignment or a commercial development project? I am quite excited to read recently that FPGAs are poised to eclipse processors for many floating point applications.Floating point arithmetic on FPGA is a complex design problem, a complex design verification problem, and a resource-hungry (expensive) implementation. Applications which need floating point arithmetic, by and large, also benefit from other capabilities provided with a full-on processor. - Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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这将是一个商业开发项目。
如果FPGA现在能够提供更多我感兴趣的翻牌。 以上来自于谷歌翻译 以下为原文 This would be a commercial development project. If FPGAs are now able to offer more flops i'm interested. |
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好吧，你没有提供任何有用的细节，但是让我来帮助你。
也： xilinx FP Logicore ip xilinx网站搜索 opencores.org搜索 - 鲍勃埃尔金德 签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。 阅读手册或用户指南。 你读过手册了吗？ 你能找到手册吗？2。 搜索论坛（并搜索网页）以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题，开始新的主题！5。 学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息（请与网页，数据表链接）.7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章，那么我一无所获。 以上来自于谷歌翻译 以下为原文 Well, you haven't provided any useful details, but let me help you. Also: xilinx FP Logicore ip xilinx site search opencores.org search - Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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FPGA和DSP是非常不同的架构。
有些例子可能是最适合的DSP。 mp3解码器就是一个例子。 FPGA显然也可以做到这一点，但可能不是我的第一个个人建议。 在某些应用中，FPGA将占据主导地位。 这是一个可能的例子：http：//www.andraka.com/V4_FP_fft.htm 一系列应用程序将取决于您的实施，经验，能力（编写HDL与DSP的C / asm非常不同），设计标准（包括成本，功耗，灵活性），设计分解和安全性。 实施等 不幸的是，在一个论坛帖子中不那么容易发帖。 您可以在这里找到一些有用的信息： http://www.bdti.com/Services/Benchmarks/OFDM [右侧的其他链接] 并且如上所述，根据精度（单次与双次），浮点不是必需的。 我想说大多数FPGA应用程序都可能是固定点，虽然浮点数肯定是可能的： http://www.xilinx.com/products/ipcenter/FLOATING_PT.htm(浮点运算符）http://www.xilinx.com/products/ipcenter/DO-DI-FPU-SP.htm（浮点运算符） PowerPC单元（单精度）） 一些应用程序（软件定义无线电）通常具有DSP，GPP（通用处理器）和FPGA，以利用它们各自的优点。 BT 以上来自于谷歌翻译 以下为原文 FPGAs and DSPs are very different architectures. There are some examples where a DSP is likely the best fit. An mp3 decoder is an example here. FPGAs can obviously do this too, but probably wouldn't be my first personal suggestion. There are some applications where an FPGA will dominate. Here's a likely example: http://www.andraka.com/V4_FP_fft.htm And a whole range of applications where it will depend on your implementation, experience, competency (writing HDL is very different than C/asm for a DSP), design criteria (including cost, power, flexibility), design decomposition & implementation, etc. And unfortunately not so easy to succintly post in a forum thread. You may find some useful information here: http://www.bdti.com/Services/Benchmarks/OFDM [other links on right side] And as stated, floating point is not necessary small depending on precision (single vs double). I would say most FPGA applications are likely fixed point, though floating point is certainly possible as well: http://www.xilinx.com/products/ipcenter/FLOATING_PT.htm (Floating-Point Operators) http://www.xilinx.com/products/ipcenter/DO-DI-FPU-SP.htm (Floating-Point Unit for PowerPC (Single Precision)) And some applications (software defined radio) often have a DSP, GPP (general purpose processor), and FPGA to leverage their respective merits. bt
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这是我打算发布的第二个链接链接：
http://www.bdti.com/bdtimark/ofdm.htm BT 以上来自于谷歌翻译 以下为原文 Here's the corected 2nd link I meant to post: http://www.bdti.com/bdtimark/ofdm.htm bt
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感谢鲍勃，我一直在进行互联网搜索，已经发现了spartan3an IP核来做FP，但尚未弄清楚IP会给我带来最快的性能，以及Saprtan3an是否能完成任务。
我目前使用开源IP FPU在Spartan3an上运行FP项目 - 它非常快，但我希望它能更快地运行，如果可以的话。 [当然] 这是令我兴奋的最新文章： http://www.eetimes.com/design/embedded/4212239/Hardware-Based-Floating-Point-Design-Flow-?Ecosystem=embedded 我对人们在FPGA中实现FP的任何经验以及他们可以分享的任何想法或评论感兴趣，包括他们遇到的成功或任何问题或失望。 以上来自于谷歌翻译 以下为原文 Thanks Bob, i have been doing internet searches, have found spartan3an IP cores to do FP, but have yet to figure out what IP would give me the fastest performance, and whether the Saprtan3an would be up the task. I have a FP project running on a Spartan3an at this time using an open source IP FPU - it is pretty fast but i'd like it to go faster if i can. [of coarse] Here's the latest article that has me excited: http://www.eetimes.com/design/embedded/4212239/Hardware-Based-Floating-Point-Design-Flow-?Ecosystem=embedded I'd be interested in any and all experience folks have had in the area of FP implementation in FPGA, and any ideas or comments they can share, including successes or any problems or disappointments they encountered. |
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谢谢tempe！
基准看起来很有趣 - 我会从那里开始。 谢天谢地，我会以单精度来表达。 我也希望我能在大多数情况下留在C / asm世界...... 我不确定我的应用程序是否更像是mp3或andraka应用程序，但我会查看链接。 它的核心基本上是一系列具有流依赖性的乘法和除法，它们看起来与硬件兼容但没有很多并行性。 裂 以上来自于谷歌翻译 以下为原文 Thanks tempe! The benchmarks look interesting - i'll start there. I'll get by with single precision thankfully. I'm also hoping i can stay in the C/asm world for the most part... I'm not sure if my application is more like an mp3 or the andraka app but i'll check out the links. It's core is basically a series of multiplys and divides with flow dependencies that look to be compatible with hardware but without a whole lot of parallelism. bobr |
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可编程逻辑擅长接口，灵活性，上市时间，降低风险等。
虽然存在C - >门流，但VHDL和Verilog是最常见的。 虽然它们可能看起来像软件一样，但它实际上是硬件设计和底层实现的概念（不同的代码如何映射到LUT，FF，BRAM，乘法器，进位链等），时序收敛，布局规划等是非常宝贵的。 加密就是一个很好的例子。 Sbox，pbox，bit swizzling等非常适合硬件实现。 典型的对称阶段（例如DES和AES）可以顺序实现，完全展开，或者介于两者之间的某种组合，以实现性能，成本，功率等的适当平衡。 许多应用程序非常平行。 自定义控制逻辑通常在状态机中实现，甚至可以在像PicoBlaze这样的嵌入式序列器中实现： http://www.xilinx.com/ipcenter/processor_central/picoblaze/picoblaze_user_resources.htm(PicoBlaze用户资源）http://forums.xilinx.com/xlnx/board?board.id=PicoBlaze（PicoBlaze论坛）http：/ /forums.xilinx.com/xlnx/board/message?board.id=PicoBlaze&thread.id=40(PicoBlaze常见问题解答） 嵌入式32位处理器（如MicroBlaze）通常很常见： http://www.xilinx.com/tools/microblaze.htm http://www.xilinx.com/support/documentation/application_notes/xapp1141.pdf(The Simple MicroBlaze微控制器概念）有些甚至超过1 ...;） 您还可以在页面顶部找到“市场解决方案”标题，以便了解客户使用零件的方式以及通常使用的应用程序。 我们的季度客户杂志中的信息很好： http://www.xilinx.com/xcell 祝你好运。 BT 以上来自于谷歌翻译 以下为原文 Programmable logic excels for interfacing, flexibility, time to market, risk reduction, etc. Although C -> gates flows exist, VHDL and Verilog are the most common. And while they may look deceptively like software, it really is hardware design and concepts like underlying implementation (how different code maps into LUTs, FFs, BRAM, multipliers, carry chains, etc.), timing closure, floorplanning, etc. are invaluable. Encryption is a great example. Sboxes, pboxes, bit swizzling, etc. is very well suited for hardware implementation. And the typical symmetric stages (e.g. DES and AES) can be sequentially implementated, fully unrolled, or some combination in between to achieve the appropriate balance of performance, cost, power, etc. Many applications are heavily parallel. And custom control logic is often implemented in state machines or even an embedded sequencer like PicoBlaze: http://www.xilinx.com/ipcenter/processor_central/picoblaze/picoblaze_user_resources.htm (PicoBlaze User Resources) http://forums.xilinx.com/xlnx/board?board.id=PicoBlaze (PicoBlaze forum) http://forums.xilinx.com/xlnx/board/message?board.id=PicoBlaze&thread.id=40 (PicoBlaze FAQ) And embedded 32-bit processors like MicroBlaze are often very common: http://www.xilinx.com/tools/microblaze.htm http://www.xilinx.com/support/documentation/application_notes/xapp1141.pdf (The Simple MicroBlaze Microcontroller Concept) Somes even more than 1... ;) You may also find the "Market Solutions" heading at the top of the page to get a good idea how custoimers are using the parts and what applications are often served. And good info here in our quarterly customer magazine: http://www.xilinx.com/xcell Good luck. bt |
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链接的EETIMES文章（由Altera应用程序管理员编写）非常出色。
您尚未说明您的设计要求（单精度FP除外）。 您的要求应该推动您的设计决策，以建立自己的IP，购买现成的IP，或购买外置处理器。 您必须做出的最重要的决定是您是否关心IEEE754合规性。 如果您没有锁定IEEE754，那么您可以灵活地设计性能和效率而不是合规性 - 并且可以实现性能与成本的巨大飞跃。 这是EETIMES文章提出的关键点之一。 下一个决定是您需要获得多少精度并保留以支持您的整体设计。 这将影响数据路径宽度和存储要求。 舍入模式也将是一个大问题（注意：截断是一种舍入模式）。 如果你没有使用DSP48模块进行归一化和对齐，另一个可以获得巨大收益的设计决策是基数4或基数8指数 - 即指数值代表（2 ^ 4）^ n（= 16 ^ n）或 （2 ^ 8）^ n（= 256 ^ n）而不是2 ^ n。 如果在4位或8位跨度中标准化或对齐，则移位器和旋转器的尺寸会缩小并加速。 我没有使用本文中提到的MathWorks / SimuLink设计流程的经验。 我不同意作者对Verilog / VHDL设计条目的解雇。 希望这可以帮助... - 鲍勃埃尔金德 签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。 阅读手册或用户指南。 你读过手册了吗？ 你能找到手册吗？2。 搜索论坛（并搜索网页）以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题，开始新的主题！5。 学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息（请与网页，数据表链接）.7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章，那么我一无所获。 以上来自于谷歌翻译 以下为原文 The linked EETIMES article (written by an Altera apps manager) is excellent. You haven't stated your design requirement (other than single-precision FP). Your requirements should drive your design decision to build your own IP, buy IP off the shelf, or buy an outboard processor. The most important decision you have to make is whether or not you care about IEEE754 compliance. If you are not locked into IEEE754, then you have the flexibility to design for performance and efficiency rather than compliance -- and huge leaps in performance vs. cost are possible. This is one of the key points made by the EETIMES article. Next decision is how much precision you need to acquire and retain to support your overall design. This will influence the data path widths and storage requirements. The rounding mode will also be a big deal (note: truncation is a rounding mode). Another design decision which can pay off tremendously, if you're not using the DSP48 blocks for normalisation and alignment, is radix 4 or radix 8 exponents -- i.e. exponent value represents (2^4)^n (=16^n) or (2^8)^n (=256^n) instead of 2^n. If you normalise or align in 4-bit or 8-bit spans,shifters and rotators shrink in size and speed up. I have no experience with the MathWorks/SimuLink design flow mentioned in the article. I don't agree with the author's dismissal of Verilog/VHDL design entry. Hope this helps... - Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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