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我已经使用了SIFLAVEFIFO异步示例，用更简单的状态机替换了状态机。当前GPIF状态机CalsDRYDATA（从THEADR3读取）在一个状态下调用另一个DRGGPIO，没有任何条件，所有的逻辑都是逻辑的。通过查看逻辑分析器，我看到适当的GPIO引脚由DrgGPIO切换，这使我相信状态机正在运行。当我使用Windows上的USB控制中心应用程序时，我可以发送2个大的1024字节数据包（它们的DMA回调被接收），之后应用程序无法发送更多的数据，并且失败消息“大容量传输失败，错误代码：997”。然而，在此之后，每一个大容量输出都失败，并且不再调用FX3上的DMA回调。
是什么导致了这个错误的发生？FX3是否认为GPIF没有足够快地从DMA缓冲器中删除内容（或者根本没有）？ 如果是这样，我应该如何在我的简单状态机中纠正这个问题？我试着在TrRe0和TreRe3之间切换DRI数据，以确保我没有混淆线程。 以上来自于百度翻译 以下为原文 I have taken the slave fifo async example, and replaced the state machine with a much simpler state machine. The current GPIF state machine calls DR_DATA (reads from Thread3) in one state then calls DR_GPIO in another, there are no conditions, everything's LOGIC_ONE. By looking at a logic analyzer I see the appropriate GPIO pin is being toggled by DR_GPIO which makes me believe that the state machine is running. When I use the USB Control Center application on windows, I can send 2 large 1024 byte packets (whose DMA callbacks are received) after which the application is unable to send any more data and fails with the message "BULK OUT transfer failed with Error Code: 997". After this however the every BULK OUT fails, and the DMA callback on the FX3 is no longer called. What causes this error to occur? Does the FX3 think the GPIF is not removing content from the DMA buffers fast enough (or at all)? If so, how should I correct this in my simple state machine? I've tried switching DR_DATA between Thread0 and Thread3 to make sure I didn't mix up the threads. 
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或者，是否有一个例子或建议的方式，从DMAIN从USB批量输出端点发送数据通过H GIF？
以上来自于百度翻译 以下为原文 Alternatively, is there an example or suggested way for DMAing from a USB BULK OUT endpoint to sending the data out throuf h GIF? |
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经过几天对GPIF总线在各种板上的实验，包括FX3 DEV板，我仍然无法获得GPIF端口来正确执行DRIMA数据动作。GPIF设计是简单的，它使用主同步模式中的16位总线。该设计包含一个具有切换DrgGPIO和ADRX数据从Socket读取的单一状态：THeRe3（我已经验证为U2P DMA描述符使用的消费线程）。我可以看到GPIO引脚与每个GPIF时钟周期切换。
使用CYFXSLFIFOASYNC C实例加载GPIF设计文件，导致错误代码997出现在两个1024字节传输被发送后，这使我认为DMA缓冲器没有被GPIF总线消耗。因此，我将函数调用到CUU3PDMACHANEL SETXFER（）中，以手动将DMA CPU缓冲区发送给GPIF。我添加了一个调用CYU3PDMACHNEURNETSUPUSTEN FUBER（），它以返回状态0结束，接着循环检查信道何时离开状态CyuU3PyDMAPPRODYORADIORY，但是信道从不这样做，并且消费者BYT E计数保持在原来的1024字节。根据文献，CyuU3PyDMAYOpRoad意味着DMA传输正在进行，但是它从未完成，并且没有出现在GPIF数据线上，GPIO引脚I设置为与DRGGPIO切换似乎在这一切期间都很好。 从这两个实验看来，GPIF控制器似乎根本不消耗缓冲器。 任何帮助都将非常感激。 我也感到沮丧，因为没有一个简单的任务，比如在任何示例或在线文档中向GPIF端口写入数据。FX3的这个功能是否已被验证？如果是这样，怎么办？ 柏树能否对此发表评论？ 以上来自于百度翻译 以下为原文 After several days of experimenting with the GPIF bus on various boards, including the FX3 dev board I still not able to get GPIF port to execute a DR_DATA action correctly. The GPIF design is a simple, it uses a 16 bit bus in master synchronous mode. The design contains a single state with a toggle DR_GPIO and a DR_DATA reading from Socket: Thread3 (which I have verified as being the consumer thread used by the U2P DMA descriptors). I can see the GPIO pin toggling with every GPIF clock cycle. Using the cyfxslfifoasync.c example to load this GPIF design file causes Error code 997 to appear after two 1024 byte transfers are sent, this made me think that the DMA buffers were not consumed by the GPIF bus. So I commented out the function calls to CyU3PDmaChannelSetXfer() to manually DMA CPU buffers to the GPIF. I added a call to CyU3PDmaChannelSetupSendBuffer(), which finishes with return status 0, followed by a loop to check to see when the channel moves away from status CY_U3P_DMA_PROD_OVERRIDE, however the channel never does, and the consumer byt e count stays at the original 1024 bytes. According to the documentation, CY_U3P_DMA_OVERRIDE means the DMA transfer is ongoing, however it never finished and nothing ever appears on the GPIF data lines, the GPIO pin I set to toggle with DR_GPIO seems to toggle just fine during all of this. From these two experiments it seems also as if the GPIF controller is not consuming buffers at all. Any help would be very greatly appreciated. I'm also disheartened to see that there are no examples for a task a simple as writing data to the GPIF port in any of the examples or online documention. Has this functionality of the FX3 been verified? If so, how? Could Cypress please comment on this? |
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显然，最简单的测试方案有时是不可行的。在完成了知道何时调用DRL数据的整个状态机之后，一切都开始工作。这使得看起来DRMA数据的定时是必需的，否则状态机可以进入奇怪的状态。
以上来自于百度翻译 以下为原文 Apparently the simplest test scenarios sometimes are the ones that don't work. After making an entire state machine that knows when to call DR_DATA everything started working. This makes it seem the timing of DR_DATA is essential otherwise the state machine can enter a weird state. |
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我也遇到了这个问题，这个问题的解决方案是什么？
为什么没有柏树评论？ 以上来自于百度翻译 以下为原文 i met the problem too, how is the solution for this case? Why no Cypress comment? |
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