使用IODELAY2来实现变量，但异步延迟

感谢Bob和mrflibble的建议。
我现在有变量，异步延迟工作。
关键问题是过分依赖SelectIO向导而不是查看它正在创建的verilog的细节。
在我的应用程序中，我不需要verilog中的一些东西，但是会导致错误。
例如，在SelectIO向导中选择“Fixed Delay”时，仍会创建clk端口，并通过自动创建的verilog中的IBUFG进行路由。
然后IODELAY2原语的clk端口接地（固定延迟的b / c）。
这个IBUFG是我很多问题的根源。
无论如何，我现在声明所有缓冲区和IODELAY2'手动'，而不使用GUI，它似乎都工作（固定和可变延迟）。
再次感谢。
在原帖中查看解决方案



以下为原文

Thanks for the advice Bob and mrflibble. I have the variable, asynchronous delay working now. The key problem was relying too much on the SelectIO Wizard and not looking into the details of the verilog it was creating. There were a bunch of things in the verilog that I didn't need for my application, but caused errors.

For example, when selecting "Fixed Delay" in the SelectIO wizard, a clk port is still created, and routed through an IBUFG in the automatically created verilog. The IODELAY2 primitive then has its clk ports grounded (b/c of the fixed delay). This IBUFG was the source of a lot of my problems.

Anyways, I now declare all the buffers and the IODELAY2 'manually', without using the GUI, and it all appears to work (both fixed and variable delay). Thanks again.
View solution in original post

IODELAY2块的任何可变延迟配置都需要IOCLK。
在搜索UG382时，IOCLK可以由BUFIO2或BUFPLL驱动。
如果可以从全局时钟（而不仅仅是输入引脚）驱动BUFIO2，那么您应该能够将SP605时钟引脚连接到全局时钟网络，以便在“远程”IO bank中使用。
试试看吧。
BUFPLL还可以驱动IOCLK网络。
BUFPLL可以从PLL驱动（参见UG382），如果你有一个可用的PLL用作时钟缓冲器，这对你的目的很好。
除了PLL输出之外，我不确定BUFPLL会接受什么作为输入。
Spartan-6时钟源/驱动器连接矩阵对我来说一直是一个模糊的主题。
如果这些建议都没有成功，并且知识渊博的人（例如Roy Miles）没有在这个帖子中做出回应，那么也许你应该打开一个webcase。
你的问题很简洁，你应该能够在短时间内获得明确的答案。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
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以下为原文

Any variable delay configuration of IODELAY2 block requires an IOCLK. Searching UG382, IOCLK can be driven by either BUFIO2 or BUFPLL.

If BUFIO2 can be driven from a global clock (and not just an input pin), then you should be able to connect the SP605 clock pin to a global clock network for use in the 'distant' IO bank. Try it and see.

BUFPLL can also drive IOCLK network. BUFPLL can be driven from a PLL (see UG382), which is fine for your purposes if you have an available PLL to act as a clock buffer. I'm not sure what BUFPLL will accept as input, other than PLL output.

The Spartan-6 clock source/drive connection matrix has always been a murky subject for me. If neither of the suggestions work out, and if someone knowledgeable (Roy Miles, for example) doesn't respond in this thread, then perhaps you should open a webcase. Your question is concise enough that you should be able to get a definitive answer in short order.

-- Bob Elkind
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再次感谢Bob的快速回复！
我认为IODELAY2需要一个IOCLK，无论它是固定的还是可变的。
这个IOCLK是校准的参考，如果你想延迟半个周期等等，只有你想要编程一个可变延迟值（编程可以来自FPGA逻辑）时才需要全局clk。
我把这些时钟混在一起吗？
除此之外，在IOWizard GUI中，选择异步延迟“灰化”BUFPLL作为选项。
我查看了Xilinx文档，并在SelectIO Interface Wizard文档中说明了这一点
“如果数据仅需要异步延迟，请选择数据未计时........如果拓扑不可用，您将无法选择它”。
因此，无论出于何种原因，我认为这意味着BUFPLL不是异步延迟的选项。
如果这是一个异步延迟，我有点困惑为什么它需要一个IOCLK。
关于你的第二点，我确实试图使用BUFIO2。
基本上我的路由是，时钟IO引脚 - > BUFG（通过PLL_base？我使用时钟向导GUI） - > BUFIO2 - > IODELAY2。
我很确定我收到的错误是“无法将多个缓冲区串联”。
所以我尝试了各种迭代，比如删除BUFG和/或BUFIO2，但我仍然遇到各种映射/ PAR错误。
如果有人有更多建议，请告诉我。
我明天再说一遍。



以下为原文

Thanks again for the prompt reply Bob!

I thought IODELAY2 required an IOCLK, whether it was fixed or variable. This IOCLK is the reference for calibration, and also if you want to delay half a bit period etc. The global clk is only needed if you want to program a variable delay value (where the programming can come from the FPGA logic). Do I have these clocks mixed up?

That aside, in the IOWizard GUI, selecting asynchronous delay "grays out" BUFPLL as an option. I looked around the Xilinx documentation, and in the SelectIO Interface Wizard documentation it says
"If the data requires an asynchronous delay only, select Data Is Not Clocked. ....... If a topology is not available, you will not be able to select it". So, for whatever reason, I took this to mean BUFPLL wasn't an option for asynchronous delays. I'm a bit puzzled why it needs an IOCLK at all though, if this is an asynchronous delay.

Regarding your second point, I did make an attempt to use BUFIO2. Basically my routing was, clock IO pins --> BUFG (via PLL_base? I used the clock wizard GUI) --> BUFIO2 --> IODELAY2. I'm pretty sure I got an error about "can't place multiple buffers in series". So I tried various iterations, like removing BUFG and/or BUFIO2, but I still got a variety of mapping/PAR errors.

If anybody has more suggestions, let me know. I'll give it another go tomorrow.

“如果可以从全局时钟（而不仅仅是输入引脚）驱动BUFIO2，
那么你应该能够将SP605时钟引脚连接到全局时钟
用于“远程”IO银行的网络。
试试吧，看看。“
我似乎记得BUFIO2确实可以由BUFG输出驱动。
那么你
可以从远处的那个IO银行输入你的时钟输入，把它变成一个全局的
时钟网，并将其用作BUFIO2的时钟输入。
然后是IO时钟
BUFIO2的输出可用作IODELAY2的时钟。
无论如何，你有没有尝试过固定延迟？
正如使用IODELAY2一样
IDELAY_VALUE属性的固定值是多少？
你可以先尝试，然后得到
放置和放置
路线。
如果这样可行，那么你至少可以修复通常情况
诸如“什么味道缓冲连接到什么”之类的问题。
之后的工作
让它可配置。
一种鸿沟和分类
征服方法。
我之所以提到这个原因，我在过去也遇到过麻烦，MAP会给我带来你提到的同样的错误。
这是因为基本上我试图把错误的东西连在一起。



以下为原文

"If BUFIO2 can be driven from a global clock (and not just an input pin),then you should be able to connect the SP605 clock pin to a global clocknetwork for use in the 'distant' IO bank. Try it and see."

I seem to recall that the BUFIO2 can indeed be driven by a BUFG output. So youcan take your clock input from that IO bank far far away, put it an a globalclock net, and use that as clock input for the BUFIO2. Then the IO clockoutput from the BUFIO2 can be used as clock for the IODELAY2.
Regardless, have you tried a fixed delay yet? As in use a IODELAY2, with afixed value for the IDELAY_VALUE attribute? You can try that first, and getthat to place & route. If that works then you have at least fixed the usualproblems like "what flavor buffer connects to what". And after that work atgetting it to be configurable. Sort of a divide & conquer approach.
The reason I mention this, I've also had troubles in the past where MAP would give me the same sort of error you mentioned. And it was because basically I tried to connect the wrong things together.

我认为IODELAY2需要一个IOCLK，无论它是固定的还是可变的。
在固定延迟模式下，IODELAY2不需要IOCLK信号。
阅读UG381第2章的IO延迟概述部分。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
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以下为原文

I thought IODELAY2 required an IOCLK, whether it was fixed or variable.

In fixed delay mode, IODELAY2 does not require an IOCLK signal. Read the IO Delay Overview section of UG381, Chapter 2.

-- Bob Elkind
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科兰，
您应该将此主题标记为“已解决”。
我会在接下来的几天内给SelectIO向导一个旋转，以复制你的结果。
您描述的SelectIO向导rsults应保证错误报告和更正。
我将打开一个webcase来设置轮子运动，并参考这个线程。
谢谢你的坚持。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
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不要在多个论坛上发布相同的问题。
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学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
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以下为原文

Corran,

You should mark this thread as 'SOLVED'.

I'll give the SelectIO wizard a spin in the next few days, to duplicate your results. The SelectIO Wizard rsults you describe should warrant a bug report and correction. I'll open a webcase to set the wheels in motion, and refer to this thread.

Thanks for your persistence.

-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.