[问答]

怎么将spartan2连接到编解码器

问答对人有帮助，内容完整，我也想知道答案 0 嗨，我正在做一个适用于并行格式数据的过滤器。所以我必须从ak4520编解码器获取串行数据并以并行格式转换8位MSB对齐。经过一些处理（低通滤波器）后，我将串行格式放回编解码器。所以我需要一个串并转换器和一个并串转换器。问题是使用下面的传输模式（我不能改变它，因为编解码器是从Xess焊接引脚配置的）我必须得到/放置20位数据或更好我可以读取/发送到第一个20位数据（编解码器的精度是20位）但是有一些“不关心”的位是32-WIDTH_OF_MY_DATA 所以我做了一些我希望工作的代码，但模拟器没有告诉我。所以我试着向你求一些帮助。在第一个模块中，问题是如果我删除计数 2）PARALLEL-TO-SERIAL 位模式与帖子头部的图片相同，我必须发送到编解码器，串行，首先是MSB，16位数据，其余32-16将是16.所以我必须发送一个LRframe总共32位，因为32是同步串行输入的时钟脉冲。并行到串行转换器的问题是ser_out与par_in数据无关，但显示出奇怪的行为。下面是代码：模块par_to_ser（// convertitore parallelo-seriale clk，//时钟为3,125mhz 64fs RESET_IN， par_in， ser_out ）; 输入clk; input reset_in; 输入[15：0] par_in; 输出ser_out; reg ser_out; wire not_reset_in; assign not_reset_in = ~reset_in; reg [5：0]柜台; 最初开始 ser_out15）开始 ser_out 数据表（1）.pdf 201 KB 以上来自于谷歌翻译以下为原文 Hi I'm doing a filter that works with parallel format data. So i have to get serial data from ak4520 codec and transform in parallel format 8 bit MSB justified. After some processing ( lowpass filter) i've to put back in serial format to the codec. So I need a serial-to-parallel converter and a parallel-to-serial converter. The problem is that using the mode of transmission below ( I can't change it because codec is configured from Xess soldering pins ) I have to get/put 20 bit of data or better I can read/send up to the firsts 20bit of data ( codec's precision is 20bit) but there are some "don't care" bit that are 32-WIDTH_OF_MY_DATA So i have done some code that I wished to work but simulator showed me not. So I try to ask you some help. In this first module the problem is that if i remove the count<8 part shift register work but every serial data, even the "don't care" go in the parallel data destroying the real first 8 bit value; if I don't remove that control, code is synthesized but in the simulator i see all x in par out //SERIAL TO PARALLEL// FIRST BIT THAT I RECEIVE IS MSB!!!! NUMBER 19 SHOWING PICTUREmodule ser_to_par( clk, // @ 3,125Mhz 64fs ser_in, reset_in, par_out ); input clk; input ser_in; input reset_in; wire not_reset_in; assign not_reset_in=~reset_in; output [7:0] par_out; reg [7:0] temporany_par; reg [7:0] par_out; reg[5:0] count; always @ (posedge clk or posedge not_reset_in) begin : PILA_VALORI if(not_reset_in==1) temporany_par<=0; else begin if(count<5'b01000) begin temporany_par <= {temporany_par[8-2:0],ser_in}; par_out = temporany_par; end count<=count +1'b1; end endendmodule 2) PARALLEL-TO-SERIAL The bit pattern is the same of the picture in the head of the post, I have to send to codec, in serial, first the MSB,16 bit of data and the rest 32-16 would be 16. So i have to send in a LRframe 32 bit in total because 32 are the clock impulses that synchronizes the serial input. The problem with the parallel-to-serial converter are that ser_out is not attinent to the par_in data but shows a strange behaviour. Below there is the code : module par_to_ser( // convertitore parallelo-serialeclk, // clock a 3,125mhz 64fsreset_in,par_in,ser_out);input clk;input reset_in;input [15:0] par_in;output ser_out;reg ser_out;wire not_reset_in;assign not_reset_in=~reset_in;reg [5:0] counter;initial beginser_out<=0;counter<=0;endalways@(posedge clk or posedge not_reset_in) beginif(not_reset_in==1) begincounter<=0;ser_out<=0;endelse beginif(counter<=15) beginser_out<=par_in[15-counter];endelse if(counter>15) beginser_out<=0;endcounter<=counter+1'b1;endendendmodule datasheet(1).pdf ‏201 KB 0
2019-6-11 09:48:00　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × asd008 该类别下有 32 个回答。邀请回答 aaaa321 该类别下有 27 个回答。邀请回答 doublelove 该类别下有 26 个回答。邀请回答 vynywrwr 该类别下有 21 个回答。邀请回答 hgjhgd 该类别下有 19 个回答。邀请回答 hanyan533 该类别下有 18 个回答。邀请回答 Jaionm 该类别下有 18 个回答。邀请回答 bwerwer 该类别下有 18 个回答。邀请回答 handsomelchcpp 该类别下有 17 个回答。邀请回答 wang2222222 该类别下有 17 个回答。邀请回答 ningee 该类别下有 16 个回答。邀请回答 binro 该类别下有 16 个回答。邀请回答 myf888 该类别下有 15 个回答。邀请回答 wznnzw 该类别下有 15 个回答。邀请回答 60user25 该类别下有 14 个回答。邀请回答 zcy615 该类别下有 14 个回答。邀请回答 wanglinhua2627 该类别下有 14 个回答。邀请回答 guotong1984 该类别下有 14 个回答。邀请回答 yhxc 该类别下有 14 个回答。邀请回答 armortech 该类别下有 14 个回答。邀请回答举报刘丹相关推荐 • 编解码器的工作原理是什么？ 2780 • 将数字麦克风连接到编解码器的正确方法是什么？ 5130 • 如何将多个AK5554编解码器与i.MX8MN SAI线集成？ 360 • 将音频编解码器整合进新一代SoC面临哪些技术挑战？ 1252 • 请问怎样去设计曼彻斯特编解码器？ 1250 • MPEG音频编解码器及其应用 1662 • 将麦克风输入与耳机控制功能连接到编解码器和正常SARADC输入引脚在Nu微®NUC505系列？ 2023 • 如何控制曼彻斯特编解码器？ 1742 • 如何将imx8mm的h.264编解码器与FreeRTOS一起使用？ 359 • 高速并行Reed-Solomon编解码器怎么实现？ 946 2个回答

答案对人有帮助，有参考价值 0 定义“奇怪的行为”。 I2S是一个简单的移位寄存器。您是在生成SCLK和LRCLK还是正在接收它们？如果接收，只需查看LRCLK上的转换并将您关心的位锁存到并行接收缓冲区中以获取输入数据，并使用下一个发送字加载输出移位寄存器。如果你正在产生，那就更容易了。 ----------------------------是的，我这样做是为了谋生。以上来自于谷歌翻译以下为原文 define "Strange behavior." I2S is a dead-simple shift register. Are you generating SCLK and LRCLK or are you receiving them? If receiving, just look for a transition on LRCLK and latch the bits you care about into your parallel receive buffer for input data, and load the outgoing shift register with the next transmit word. If you are generating, it's even easier. ----------------------------Yes, I do this for a living.

2019-6-11 10:05:07 评论举报黄淳

答案对人有帮助，有参考价值 0 嘿，我正在为系统和编解码器生成时钟模块预分频器（clk，//从pll输入50mhz输入 RESET_IN， twelwe_dot_five_M， tre_dot_one_twenty_five_M， forty_eight_kilo_M）; 输入clk; input reset_in; wire not_reset_in; assign not_reset_in = ~reset_in; 输出twelwe_dot_five_M; 输出tre_dot_one_twenty_five_M; // 64fs - >单个位的时钟输出forty_eight_kilo_M; //样本的周期 - > iir的时钟 reg [9：0]柜台; 初始反击我没有使用I2S，在我将I2S模式表示为不同模式之前提到的编解码器文档中。我只能使用我在previuos帖子中发布的比特序列。 1）SERIAL_TO_PARALLEL 我发布了模拟器的输出您可以看到的问题是，即使在重置之后，par_output的所有位都是x。我重新发布了代码 module ser_to_par（//串行并行转换器 clk，// 3,125Mhz 64fs ser_in，//串行数据输入 RESET_IN， par_out ）; 输入clk; 输入ser_in; input reset_in; wire not_reset_in; assign not_reset_in = ~reset_in; 输出[7：0] par_out; reg [7：0] temporany_par; reg [7：0] par_out; reg [5：0]计数; 总是@（posedge clk或posedge not_reset_in）开始如果（not_reset_in == 1）开始 temporany_par 2）PARALLEL_TO_SERIAL 模拟输出是奇怪的行为可能是因为我使用了一个糟糕的测试wawefile，我重新创建它改变每个32clk节拍par_in似乎工作但问题是第一个样本没问题，但第二个没有！（看看wawe的结尾）我不知道为什么。你可以用更长的时间模拟吗？我尝试过很长时间的测试，但是对于modelsim的学生版我不能做更多代码是模块par_to_ser（// paralll到串行转换器 clk，// 3,125mhz 64fs RESET_IN， par_in， ser_out ）; 输入clk; input reset_in; 输入[15：0] par_in; 输出ser_out; reg ser_out; wire not_reset_in; assign not_reset_in = ~reset_in; reg [5：0]柜台; 最初开始 ser_out15）开始 ser_out 以上来自于谷歌翻译以下为原文 Hey, I'm generating clock for system and codec with module prescaler(clk, //clock a 50mhz input from pll reset_in, twelwe_dot_five_M, tre_dot_one_twenty_five_M, forty_eight_kilo_M);input clk;input reset_in;wire not_reset_in;assign not_reset_in=~reset_in;output twelwe_dot_five_M;output tre_dot_one_twenty_five_M;//64fs -->clock of a single bitoutput forty_eight_kilo_M; // sample's period --> clock of iirreg [9:0] counter;initial counter<=0;always @(posedge clk or posedge not_reset_in)//reset active lowif (not_reset_in==1'b1) counter <=10'b0;else begincounter <=counter + 1'b1;endassign twelwe_dot_five_M = counter[1];//mclk master clock codecassign tre_dot_one_twenty_five_M = counter[3]; // sclkassign forty_eight_kilo_M = counter[9]; //lrckendmodule I'm not using I2S, in the codec documentation i allegated before I2S mode is represented as a different mode. I can use only the bit sequence i posted in the previuos post. 1)SERIAL_TO_PARALLEL I post the output of simulator The problem as you can see is that all the bits of the par_output are x , even after a reset. I repost the code module ser_to_par( // serial parallel converteerclk, // 3,125Mhz 64fsser_in,// serial data inputreset_in,par_out);input clk;input ser_in;input reset_in;wire not_reset_in;assign not_reset_in=~reset_in;output [7:0] par_out;reg [7:0] temporany_par;reg [7:0] par_out;reg[5:0] count;always @ (posedge clk or posedge not_reset_in)begin if(not_reset_in==1)begin temporany_par<=0;endelse begin if(count<5'b01000) begintemporany_par <= {temporany_par[8-2:0],ser_in};par_out = temporany_par;end count<=count +1'b1;endendendmodule 2) PARALLEL_TO_SERIAL The simulation output is Strange behaviuor was maybe because I used a bad test wawefile, I've recreated it changing every 32clk beats par_in and seems to work but a problem is that the first sample go ok but the second not! ( look at the end of the wawe) and I don't know why. Could you simulate with a longer time? I've tryed with a very long test waweform but with the student version of modelsim I can't do more code is module par_to_ser( // paralll to serial converterclk, // 3,125mhz 64fsreset_in,par_in,ser_out);input clk;input reset_in;input [15:0] par_in;output ser_out;reg ser_out;wire not_reset_in;assign not_reset_in=~reset_in;reg [5:0] counter;initial beginser_out<=0;counter<=0;endalways@(posedge clk or posedge not_reset_in) beginif(not_reset_in==1) begincounter<=0;ser_out<=0;endelse beginif(counter<=15) beginser_out<=par_in[15-counter]; // MSBendelse if(counter>15) beginser_out<=0; // 16 bit don't careendcounter<=counter+1'b1;endendendmodule

2019-6-11 10:13:07 评论举报刘刚