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设备：Spartan 6,144 QFP，速度等级：3 经验：刚刚从使用Altera产品转向Xilinx产品。 使用FPGA作为项目的一部分1年。 项目： 通过并行LVDS接口将上述Spartan 6连接到几种不同类型的ADC（1 GSa至500 MSa）。 ADC的时钟由FPGA生成，与并行接口位于同一个bank中。 问题： 我正在使用的ADC品牌没有利用时钟的两个边缘进行采样。 结果是，如果我想使用GSa ADC，我必须生成1 GHz差分时钟。 我开始得出这样的结论：在任何情况下单独使用Spartan 6都是不可能的（需要外部1：2 PLL）。 题： 我的结论是否正确无法从斯巴达6输出1 GHz时钟？ 我已经查看了DS 162表25，看起来很清楚差异IO的功能是什么，但也许这个表不是故事的结尾？ 我只是问，因为内部PLL能够产生1.05 GHz的频率，根据我的理解，这对于为结构提供时钟来说太快了。 如果是这种情况，那么我不知道为什么会这样做。 除了使用外部PLL（价格为5美元或更高）之外，还有另一种方法，例如使用内置收发器的模型吗？ 也许本地GHz振荡器可能是合适的。 感谢您的时间，这些论坛是一个很棒的工具。 埃里克 以上来自于谷歌翻译 以下为原文 Background: Device: Spartan 6, 144 QFP, Speed Grade: 3 Experience: Just switched from using Altera products to Xilinx products. 1 year of using FPGAs as part of projects. Project: Interfacing the Spartan 6 mentioned above to a few different flavors of ADCs ( 1 GSa to 500 MSa ) over a parallel LVDS interface. The clock for the ADC is generated from the FPGA and is in the same bank as the parrallel interface. Problem: The ADC brand I am using does not utilize both edges of the clock for sampling. The result is that I have to produce a 1 GHz differential clock if I want to use the GSa ADC. I am beginning to come to the conclusion that this will not be possible under any circumstances with the Spartan 6 alone (external 1:2 PLL required). Question: Am I correct in my conclusion that there is not a way to output a 1 GHz clock from the spartan 6? I have looked at DS 162 table 25 and it seems pretty clear about what the differential IO are capible of, but perhaps that table is not the end of the story? I am only asking because the internal PLL is capible of generating 1.05 GHz which, from my understanding, is too fast for clocking the fabric. If that is the case, then I do not know why that is made possible. Besides using an external PLL ($5 or more a pop), is there another way such as using a model with a built in tranciever? Perhaps a local GHz oscillator might be appropriate. Thank you for your time, these forums are a great tool. Eric 
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使用ISERDES / OSERDES块，Spartan-6 -3显然能够实现1Gb /秒I / O（实际上是1.08Gb /秒）。
结构时钟限制为400MHz（参见BUFGMUX规范，表48）。 正如您所描述的那样，这对您的设计来说不是问题 - 结构将以250MHz或更低的频率运行（假设输出串行化为4：1），可能为125MHz（假设8：1序列化）。 I / O时钟的频率限制比全局结构时钟高得多 - 高达1.08 GHz，具体取决于使用的时钟分配缓冲区。 典型的ISERDES / OSERDES设计在PLL中生成I / O时钟，并使用BUFPLL缓冲器将I / O时钟分配给IOLOGIC。 见表52。 因此，时钟生成和数据输出在-3速度等级部件的保证工作范围内。 仍然缺少的唯一一个难题是将1GHz I / O时钟转发到输出引脚。 通过使用OSERDES模块转发时钟，限制为540MHz（1.08 Gb / sec除以2）。 将I / O时钟转发到输出引脚的典型方法是使用ODDR2模块。 目前的Spartan-6数据表很少提到ODDR2的性能特征。 在表25中，ODDR2模块规格为800Mb / s max，转换为400MHz时钟。 但请注意，此规范基于BUFG时钟缓冲器的使用，其限制为400MHz保证操作（表48）。 如果使用BUFPLL输出计时，ODDR2模块可能具有1.08 GHz的性能。 如果确实如此，这可能不是第一次发现S6数据表缺少特定的有用性能规格，并且由于某些从属条件的限制，引用的性能低于实际性能。 如果ODDR2模块能够承载1.08GHz的时钟频率 - 而且我对此情况有点确信 - 还有两个障碍需要克服： 1. LVDS输出缓冲器能否传播1GHz时钟，这相当于2Gb / s比特流的带宽？ 2. Spartan-6器件系列中使用的引线键合封装在飞行时间（偏斜）方面表现出引脚到引脚的变化，这在1Gb / sec数据速率下是显着的。 这对于单比特串行接口来说不是问题，但必须考虑到并行接口，例如您为设计所描述的内容。 在我写这篇文章的那个周末开始了，大多数了解数据表规范背后数据的人现在都在家里与亲人一起放松。 在您庆祝或放弃所有希望之前，等待周一或周二让真正的Xilinx大师回答您的具体问题。 话虽如此，你描述的设计是积极的。 您不仅在接近其数据表性能限制的情况下操作Spartan-6器件，而且电路板设计将是艰苦的。 我告诉过你我在这个问题上所知道的一切......等等。 - 鲍勃埃尔金德 签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。 阅读手册或用户指南。 你读过手册了吗？ 你能找到手册吗？2。 搜索论坛（并搜索网页）以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题，开始新的主题！5。 学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息（请与网页，数据表链接）.7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章，那么我一无所获。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Spartan-6 -3 is plainly and clearly capable of 1Gb/sec I/O (actually, 1.08Gb/sec) using the ISERDES/OSERDES blocks. The fabric clock is limited to 400MHz (see the BUFGMUX spec, Table 48). As you've described it, this is not a problem for your design -- the fabric will be operating at 250MHz or less (assuming 4:1 output serialisation), possibly 125MHz (assuming 8:1 serialisation). The I/O clock has a much higher frequency limit than global fabric clock -- up to 1.08 GHz, depending on which clock distribution buffers are used. Typical ISERDES/OSERDES designs generate the I/O clock in a PLL, and distribute the I/O clock to the IOLOGIC with BUFPLL buffers. See Table 52. So clock generation and data output is within the guaranteed operating range of -3 speed grade parts. The only piece of the puzzle still missing is the forwarding of the 1GHz I/O clock to an output pin. By using an OSERDES block to forward the clock, you are limited to 540MHz (1.08 Gb/sec divided by 2). The typical method of forwarding an I/O clock to an output pin is to use an ODDR2 block. The current Spartan-6 datasheet has very few mentions of the ODDR2 performance characteristics. In Table 25, the ODDR2 block is spec'd at 800Mb/s max, which translates to 400MHz clock. But notice that this spec is based on the use of BUFG clock buffers, which are limited to 400MHz guaranteed operation (Table 48). The ODDR2 block might well be capable of 1.08 GHz performance if clocked with BUFPLL outputs. If this is indeed the case, this wouldn't be the first time that the S6 datasheet was found to be missing specific useful performance specifications, and the quoted performance was lower than actual performance due to a limitation imposed by some subordinate condition. If the ODDR2 block is capable of bearing a clock rate of 1.08GHz -- and I'm somewhat confident that this is the case -- there are two more obstacles to be overcome: 1. Can an LVDS output buffer propagate a 1GHz clock, which is equivalent bandwidth to a 2Gb/s bit stream? 2. The wire-bond packaging used in the Spartan-6 device family exhibits pin-to-pin variations in flight time (skew) which are significant at 1Gb/sec data rates. This isn't a problem for single-bit serial interfaces, but it must be considered for bit-parallel interfaces such as what you've described for your design. The weekend is beginning as I write this, and most of the folks who understand the underlying data behind the datasheet specifications are now relaxing at home with their loved ones. Wait for Monday or Tuesday for a true Xilinx guru to answer your specific questions before you either celebrate or abandon all hope. Having said that, the design you describe is aggressive. Not only are you operating the Spartan-6 device near its datasheet performance limits, but the circuit board design will be painstaking. I have told you everything I know on this subject... and more. -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.View solution in original post |
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使用ISERDES / OSERDES块，Spartan-6 -3显然能够实现1Gb /秒I / O（实际上是1.08Gb /秒）。
结构时钟限制为400MHz（参见BUFGMUX规范，表48）。 正如您所描述的那样，这对您的设计来说不是问题 - 结构将以250MHz或更低的频率运行（假设输出串行化为4：1），可能为125MHz（假设8：1序列化）。 I / O时钟的频率限制比全局结构时钟高得多 - 高达1.08 GHz，具体取决于使用的时钟分配缓冲区。 典型的ISERDES / OSERDES设计在PLL中生成I / O时钟，并使用BUFPLL缓冲器将I / O时钟分配给IOLOGIC。 见表52。 因此，时钟生成和数据输出在-3速度等级部件的保证工作范围内。 仍然缺少的唯一一个难题是将1GHz I / O时钟转发到输出引脚。 通过使用OSERDES模块转发时钟，限制为540MHz（1.08 Gb / sec除以2）。 将I / O时钟转发到输出引脚的典型方法是使用ODDR2模块。 目前的Spartan-6数据表很少提到ODDR2的性能特征。 在表25中，ODDR2模块规格为800Mb / s max，转换为400MHz时钟。 但请注意，此规范基于BUFG时钟缓冲器的使用，其限制为400MHz保证操作（表48）。 如果使用BUFPLL输出计时，ODDR2模块可能具有1.08 GHz的性能。 如果确实如此，这可能不是第一次发现S6数据表缺少特定的有用性能规格，并且由于某些从属条件的限制，引用的性能低于实际性能。 如果ODDR2模块能够承载1.08GHz的时钟频率 - 而且我对此情况有点确信 - 还有两个障碍需要克服： 1. LVDS输出缓冲器能否传播1GHz时钟，这相当于2Gb / s比特流的带宽？ 2. Spartan-6器件系列中使用的引线键合封装在飞行时间（偏斜）方面表现出引脚到引脚的变化，这在1Gb / sec数据速率下是显着的。 这对于单比特串行接口来说不是问题，但必须考虑到并行接口，例如您为设计所描述的内容。 在我写这篇文章的那个周末开始了，大多数了解数据表规范背后数据的人现在都在家里与亲人一起放松。 在您庆祝或放弃所有希望之前，等待周一或周二让真正的Xilinx大师回答您的具体问题。 话虽如此，你描述的设计是积极的。 您不仅在接近其数据表性能限制的情况下操作Spartan-6器件，而且电路板设计将是艰苦的。 我告诉过你我在这个问题上所知道的一切......等等。 - 鲍勃埃尔金德 签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。 阅读手册或用户指南。 你读过手册了吗？ 你能找到手册吗？2。 搜索论坛（并搜索网页）以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题，开始新的主题！5。 学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息（请与网页，数据表链接）.7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章，那么我一无所获。 以上来自于谷歌翻译 以下为原文 Spartan-6 -3 is plainly and clearly capable of 1Gb/sec I/O (actually, 1.08Gb/sec) using the ISERDES/OSERDES blocks. The fabric clock is limited to 400MHz (see the BUFGMUX spec, Table 48). As you've described it, this is not a problem for your design -- the fabric will be operating at 250MHz or less (assuming 4:1 output serialisation), possibly 125MHz (assuming 8:1 serialisation). The I/O clock has a much higher frequency limit than global fabric clock -- up to 1.08 GHz, depending on which clock distribution buffers are used. Typical ISERDES/OSERDES designs generate the I/O clock in a PLL, and distribute the I/O clock to the IOLOGIC with BUFPLL buffers. See Table 52. So clock generation and data output is within the guaranteed operating range of -3 speed grade parts. The only piece of the puzzle still missing is the forwarding of the 1GHz I/O clock to an output pin. By using an OSERDES block to forward the clock, you are limited to 540MHz (1.08 Gb/sec divided by 2). The typical method of forwarding an I/O clock to an output pin is to use an ODDR2 block. The current Spartan-6 datasheet has very few mentions of the ODDR2 performance characteristics. In Table 25, the ODDR2 block is spec'd at 800Mb/s max, which translates to 400MHz clock. But notice that this spec is based on the use of BUFG clock buffers, which are limited to 400MHz guaranteed operation (Table 48). The ODDR2 block might well be capable of 1.08 GHz performance if clocked with BUFPLL outputs. If this is indeed the case, this wouldn't be the first time that the S6 datasheet was found to be missing specific useful performance specifications, and the quoted performance was lower than actual performance due to a limitation imposed by some subordinate condition. If the ODDR2 block is capable of bearing a clock rate of 1.08GHz -- and I'm somewhat confident that this is the case -- there are two more obstacles to be overcome: 1. Can an LVDS output buffer propagate a 1GHz clock, which is equivalent bandwidth to a 2Gb/s bit stream? 2. The wire-bond packaging used in the Spartan-6 device family exhibits pin-to-pin variations in flight time (skew) which are significant at 1Gb/sec data rates. This isn't a problem for single-bit serial interfaces, but it must be considered for bit-parallel interfaces such as what you've described for your design. The weekend is beginning as I write this, and most of the folks who understand the underlying data behind the datasheet specifications are now relaxing at home with their loved ones. Wait for Monday or Tuesday for a true Xilinx guru to answer your specific questions before you either celebrate or abandon all hope. Having said that, the design you describe is aggressive. Not only are you operating the Spartan-6 device near its datasheet performance limits, but the circuit board design will be painstaking. I have told you everything I know on this subject... and more. -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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Bob对IO中的各种元素有一个非常好的描述，但最重要的是，它不可能在Spartan-6或我所知道的任何其他FPGA中输出1GHz时钟。
要求高于1 GHz或2 Gbps需要MGT，这不会与IO对齐。如果您不想添加外部时钟PLL倍频器，我建议寻找另一个支持DDR时钟速率的ADC。 ------您是否尝试在Google中输入问题？ 如果没有，你应该在发布之前。太多结果？ 尝试添加网站：www.xilinx.com 以上来自于谷歌翻译 以下为原文 Bob had a very nice description of a variety of elements in the IO, but the bottom line is that it is not possible to output a 1GHz clock in Spartan-6 or any other FPGA that I am aware of. Getting above 1 GHz or 2 Gbps requires a MGT and this would not be aligned to the IO. I would recommend finding another ADC that supports a DDR clock rate if you don't want to add the external clock PLL multiplier.------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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非常感谢您的回复。
鲍勃，你的回答非常有启发性，非常感谢。 就产生1 GHz而言，除了将其从芯片中取出之外，我不需要考虑其他任何事情。 ADC发出它自己的锁相DDR时钟，用于读取并行LVDS输出，这将是一个“舒适”的500 MHz。 可能与否，虽然我已经考虑到我为使GHz版本运行所做的更改，但我已经自行辞职以启动并运行500 MHz版本。 我是Xilinx工具的新手，因此，我应该研究一个现实问题。 我实际上已经设计了电路板，并且正在使用当前的真实设备。 我可以诚实地说，为10个阻抗匹配的差分对创建几何结构比试图找出解决这个问题的方法更有趣。 以上来自于谷歌翻译 以下为原文 Thank you so much for your responses. Bob, your response was very enlightening and much appreciated. As far as generating 1 GHz goes, I do not have to consider anything else other than getting it out of the chip. The ADC emits it's own phase locked DDR clock for reading the parallel LVDS outputs which would be a "comfortable" 500 MHz. Possible or not though, I have resigned by self to getting the 500 MHz version up and running before I even think about the changes I make to get the GHz version running. I am new to Xilinx's tools and as such, I should be working on a realistic problem. I have actually already designed the board and am working with the real device currently. I can honestly say that creating the geometry for the 10 impedance matched differential pairs was more fun than trying to figure out a solution to this problem. |
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