请问怎么才能改进Spartan-6 DCM_CLKGEN的抖动容限？

我绝对希望有一些改进的抖动容限！
有没有人对这个明显的异常有任何见解？
我不会称之为异常。
这更像是过度简化的建议或缺少一组性能图表。
抖动容限是传递函数，而不是逻辑切换功能。
表55未标记为“所需操作条件”，标记为“推荐操作条件”。
我的猜测是：在DCM_CLKGEN模式下运行，DCM具有 - 设计 - 更大的输入抖动容限。
如果输入抖动容限的增加量化并发布在数据表（DS162）中，则必须根据该规范测试每个生产部件。
对于（主要）数字逻辑器件的生产线来说，这是一项昂贵的模拟测试，即使可以简明地定义定量规范和测试程序。
毕竟，有关于时钟抖动，定义和测量实践的全部书籍。
话虽如此，阅读有关DCM_SP与DCM_CLKGEN模式的抖动容限差异的描述会很有意思，但是当Xilinx的知识产权警察“清理”可能披露或暗示专有IP的任何内容的描述时（即
商业机密），毕竟，描述可能并不那么有趣。
- 鲍勃埃尔金德
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以下为原文

I definitely would like some of that improved jitter tolerance! Does anyone have any insights into this apparent anomaly?

I wouldn't call this an anomaly. It's more like a case of oversimplified recommendations or a missing set of performance graphs. Jitter tolerance is a transfer function, not a logic switching function.

Table 55 is not labeled "Required Operating Conditions", it's labeled "Recommended Operating Conditions".

My guess is this: Operating in DCM_CLKGEN mode, the DCM has -- by design -- greater input jitter tolerance. If the increase in input jitter tolerance is quantified and published in the datasheet (DS162), then each and every production part must be tested against that specification. That's an expensive analogue test for the production lines of a (primarily) digital logic device, even if a quantitative spec and test procedure could be concisely defined. After all, there are entire books written on the subject of clock jitter, its definitions, and measurement practices.

Having said that, it would be interesting to read a description of the differences in jitter tolerance for DCM_SP vs. DCM_CLKGEN mode, but by the time Xilinx' IP police 'cleanse' the description of anything which might disclose or hint at proprietary IP (i.e. trade secrets), the description might not be all that interesting, after all.

-- Bob Elkind
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