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你好，
我正在研究一个项目，我们用一个外部时钟源在GPIF模式中把AptiNA光学传感器连接到FX2。 我们连接 RealIX有效到RDY0， 框架对RDY1有效 到IFCK的像素时钟 像素数据总线到D0—D7 FX2的引脚。 它在CY3681-开发工具包上工作得很好，带有128个引脚的FX2的一个相当旧的修订。 然而，在另一块板上，有了56个引脚的新FX2LP，当我从外部时钟源（传感器生成的像素时钟）发出GPIF时，GPIF波一旦启动，就永远不会完成。 当我实验切换GPIF时钟源到内部时钟，波将完成。在这种情况下，数据是无意义的（因为GPIF没有同步到像素时钟），但是我可以看到，我的决定状态（等待帧的开始和行的开始）工作… 在两个板上，我已经将逻辑分析仪连接到FX2的各个引脚，并且可以看到来自传感器的信号是相同的。在开发板上，我看到波浪的状态也在变化。我不能用FX2的56针版本在另一个板上进行验证。 谁能给我一些提示，我应该去哪里看呢？ FX2的不同版本之间有什么特别的区别，这可能会导致这样的问题吗？ 非常感谢您的帮助。 以上来自于百度翻译 以下为原文 Hi, I'm working on a project, where we connected an Aptina optical sensor to the FX2 in GPIF-mode with external clock-source. We connected the LINE_VALID to RDY0, the FRAME_VALID to RDY1 the pixel-clock to the IFCLK and the pixel-data bus to D0-D7 pins of the FX2. It works really well on the CY3681 developmen-kit with an rather old revision of the FX2 with 128-pins. However on other board, with rather new FX2LP with 56-pins, the GPIF-wave once started will never get done, when I source the GPIF from the external clock-source (sensor generated pixel-clock). When I experimentally switch the GPIF clock-source to internal clock, the wave will get done. In this case, the data are nonsense (because the GPIF is not synchronized to the pixel-clock) but I can see that my decision states (waiting for the start of the frame and start of the line) works... On both boards I have connected the logic analyzer to the respective pins of the FX2 and can see that the signals from the sensor are the same. On the development-board, I see the states of the wave changing too. This I can't verify on the other board with the 56-pin version of FX2. Can anybody please give me any hint, where else I should look? Are there any specific differences between the different versions of the FX2, that might cause such a problem? Any help is greatly appreciated. 
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你好，
如果您使用的是来自外部源的接口时钟（在您的情况下是图像传感器），那么在配置IFCONFIG.7之前，它应该是可用的。在固件集IFCONFIG 7＝0之前必须存在外部IFCK源。 请检查你是否符合这个条件。 谢谢， Sai Krishna。 以上来自于百度翻译 以下为原文 Hi, If you are using interface clock from external source (image sensor in your case) then it should be available before you configure IFCONFIG.7. The external IFCLK source must be present before the firmware sets IFCONFIG.7 = 0 Please check whether you are meeting this condition or not. Thanks, Sai Krishna. |
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2019-6-11 09:15:10
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你好，
谢谢你的快速回复。 在此期间，我一直在寻找自己的两个版本的FX2（128针对56针）和两个板的差异。 设置之间有一个显著的区别：128引脚开发板（工作）是总线供电，56针（不工作）板是自供电的。这可能解释GPIIFITIE（）在像素时钟稳定之前被调用…我来查一下。 还有一件事引起了我的注意，我正在检查GPIF设计器中波形的配置。 我的波使用TCXPIER/RDY5信号。在启动波之前，我正在设置期望的转换计数，并且在波中，我正在检查TCXPIR信号以再次切换到空闲状态。但是，当我将GPIF设计器中的部分设置更改为56引脚的FX2时，该信号在框图中不再可用。 我没有发现任何具体的信息在TRM，你能告诉我，如果TCXPiar信号是可用的FX2LP与56针？ 谢谢你的任何帮助。 以上来自于百度翻译 以下为原文 Hi, thanks for the quick reply. In the meantime, I've been searching myself for the differences of the two versions of the FX2 (128-pin vs. 56-pin) and the two boards. There is one significant difference between the setups: the 128-pin development-board (working) is bus-powered and the 56-pin (not working) board is self-powered. That would maybe explain that the GpifInit() would get called before the pixel-clock gets stable... I will check that. There is one other thing, that caught my attention, while I was checking the configuration of the wave in the GPIF-Designer. My wave uses the TCxpire/RDY5 signal. Before I start the wave, I'm setting the desired transation count and within the wave I'm checking the TCxpire signal to switch to the idle-state again. However, when I change the part-setting in the GPIF-Designer to the FX2 with 56-pin, this signal is not available anymore in the block-diagram. I didn't find any specific information in the TRM, can you please tell me, if the TCxpire signal is available on an FX2LP with 56-pins? Thanks for any help in advance. |
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你好，
RDY5/TCExpRE信号在FX2LP的56引脚封装中不可用。 当做， 加亚特里 以上来自于百度翻译 以下为原文 Hi, RDY5/ TCExpire signal is not available in 56 pin package of FX2LP. Regards, Gayathri |
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你好，
因此，基本上，取决于传输计数（内部TCXPIR）机制的任何波将用FX2的变体进行NoCH工作。 我说的对吗？ 当做， Pavol。 以上来自于百度翻译 以下为原文 Hi, so basically, any wave depending on the transmission count (internal TCxpire) mechanism will noch work with that variant of FX2. Am I right? Regards, Pavol. |
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你好，
很抱歉造成的混乱。我的意思是RDY5信号（外部RDY信号）在56引脚封装中不可用。然而，TCXpire是一个内部RDY信号，即使在56引脚封装也是可用的。如果在GPIF设计器中选择56引脚FX2包，则在决策状态下使用以下选项作为RDY信号：RDY0、RDY1、TCXpire、FIFOFACH、IntRdy。 当做， 加亚特里 以上来自于百度翻译 以下为原文 Hi, SOrry for the confusion caused. What I meant was RDY5 signal (an external RDY signal) is not available in 56 pin package. However, TCXpire being an internal RDY signal, is available even in 56 pin package. If you choose 56 pin FX2 package in GPIF designer, you have the following options to use as RDY signals in a decision state: RDY0, RDY1, TCXpire, FIFOflag, IntRdy. Regards, Gayathri |
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GPF设计器的PFA截图。
FX2Y56JPG 59.1 K 以上来自于百度翻译 以下为原文 PFA screenshots from GPIF designer.
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你好，
谢谢你的回复。我只是想知道，因为我的波（使用TCXPIR）似乎与内部时钟源，甚至与56针FX2。 昨天，我正在尝试GPIF init。我将调用从GdIFIN（）转移到TDyIn（）到TDyPayPLE（），并将它推迟到只在主机的StestSo配置请求之后调用。在这一点上，像素时钟（外部GPIF时钟源）应该是稳定的。然而，我仍然看不见波浪的终结。我甚至简化了波只有两个决定点，它识别图像的第一行的开始，然后GPIF应该空闲（完成）。正如我之前写的，我从逻辑分析仪上看到传感器的信号，它们很好。然而，传感器时钟太快，无法在分析仪上正确地看到它。另一方面，在另一块板上的交叉检查表明波浪起作用。 有没有其他人的想法，这可能会导致问题？ 任何帮助或建议都非常感谢。 Pavol。 以上来自于百度翻译 以下为原文 Hi, thanks for the reply. I was just wondering because my wave (using TCxpire) seem to work with the internal clock-source even with the 56-pin FX2. Yesterday, I was experimenting with the GPIF init. I moved the call to GpifInit() from TD_init() to TD_poll() and postponed it to get called only after SetConfiguration-Request from the host. At that point the pixel-clock (external GPIF clock-source) should definitely be stable. However, I still couldn't see that the wave finishes. I even simplified the wave to have only two decision points, which recognizes the start of the first line of the image and then GPIF should go Idle (done). As I wrote earlier, I see the signals from the sensor on the logic analyzer and they are well. However the sensor clock is too fast to see it properly on that analyzer. On the other side, cross-checking on the other board shows that the wave works... Has anyone any further ideas, that could cause the problem? Any help or suggestions are appreciated very much. Pavol. |
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你好，
你使用的像素时钟的值是多少？是在5到48兆赫的范围内吗？ 当做， 加亚特里 以上来自于百度翻译 以下为原文 Hi, What is the value of Pixel clock which you are using? Is it in the range 5 - 48MHz? Regards, Gayathri |
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嗨，伙计们，
只是想报告现在一切都很好。问题是在“GPIF设计器”中设置“同步RDY到IFCK”选项。我在开发板上进行了实验（用128针版本），并禁用了选项，看看GPIF对RDY输入信号的反应速度更快，当我移到另一个板（56个FX版本的FX2）时，它就被禁用了。 当我启用这个选项时，所有的工作都在板上与56个FX2版本的外部时钟源一起工作。当我离开它时，GPIF没有看到完成波，即使它似乎对开发板没有任何影响。 在GPIF与两个FX2版本之间的外部时钟源之间的工作方式似乎有所不同，这取决于选项。 谢谢你的想法和时间。 当做， Pavol。 以上来自于百度翻译 以下为原文 Hi guys, just wanted to report that everything works well now. The problem was the setting of the "Sync RDY to IFCLK" option in the "GPIF Designer". I was experimenting with that on the developent board (with the 128-pin version) and disabled the option to see if GPIF reacts faster to the RDY-input signals and left it disabled as I moved to the other board (with 56-pin version of the FX2). Everything works well and stable on the board with the 56-pin version of FX2 with the external clock source, when I enable this option. When I leave it disabled the GPIF doesn't seen to complete the wave there, even if it doesn't seem to have any impact on the development board. There seem to be a difference in how the GPIF works with external clock source between the two FX2 versions, depending on the option . Thank you for the ideas and time. Regards, Pavol. |
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