片外终端取决于频率吗？

>片外终端取决于频率？
如果是，频率是多少？
不，这取决于PCB走线的长度和信号边沿的速度。
一个非常粗略的经验法则是“当沿着PCB走线行进的时间超过边缘转换时间的三分之一时，您需要终止”。
例如：对于1ns过渡和PCB走线，速度为0.5 C，经验法则是当走线长度超过50mm时需要终止。
PCB走线的速度可以根据其几何尺寸和PCB基板的Er来轻松计算。
像这样的计算器可以很容易：
http://emclab.mst.edu/pcbtlc2/microstrip.html
通过使用HyperLynx甚至Spice等模拟器，您可以比经验法则做得更好。



以下为原文

> Off-Chip termination depends on frequency? if yes what is the frequency?

No, it depends on the length of the PCB trace and the speed of the signal edges.

A very rough rule of thumb is "you need termination when the time to travel down the PCB trace exceeds one third of the edge transition time". For example: with 1ns transitions and PCB traces with a speed of 0.5 C the rule of thumb is that termination is required when the traces are longer than 50mm.

The speed of your PCB traces can easily be calculated from their geometry and the Er of the PCB substrate. Calculators like this make it easy:

http://emclab.mst.edu/pcbtlc2/microstrip.html

You can do much better than the rule of thumb by using simulators like HyperLynx or even Spice.

更新：请忽略。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

UPDATED: please ignore.

-- Bob Elkind
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2. Search the forums (and search the web) for similar topics.
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更新：请忽略。
- 鲍勃埃尔金德



以下为原文

UPDATED: please ignore.

-- Bob Elkind

“FP_VTT_50”表示远端并联VTT终端 - 即PCB走线远端的VTT 50欧姆电阻，而不是FPGA（源）端。
> FP_VTT_50是一种终止形式，它是FPGA的内部（片内）。
参见UG381，标题为“I / O端接技术”的部分和图1-18。
我读的那个数字与Bob不同，据我所知，图1-18显示了FPGA外部的终端方案。
内部端接选项如图1-4至1-8所示。
内部选项的名称如UNTUNED_50，UNTUNED_SPLIT_75等。
最好的祝福，
斯蒂芬



以下为原文

"FP_VTT_50" means farparallel VTT termination - ie a 50 ohm resistor to VTT at the far end of the PCB trace, not at the FPGA (source) end.

> FP_VTT_50 is a form of termination which is internal(on-chip) to the FPGA. See UG381, section titled " I/O Termination Techniques" and Figure 1-18.

I read that figure differently Bob, as I understand it Fig 1-18 shows termination schemes that are external to the FPGA. Internal termination options are shown in Figs 1-4 through 1-8. The internal options have names like UNTUNED_50, UNTUNED_SPLIT_75 etc.

Best regards,
Stephen

斯蒂芬是对的，我错了。
FP_VTT_50指的是外部终端，而不是内部终端。
换句话说，FP_VTT_50终止属性的存在与否不会影响FPGA输出缓冲区。
正如斯蒂芬准确解释的那样，内部（或外部）终止的需要取决于您的应用。
如果需要终止，终止类型也取决于您的应用程序。
有关一些常见端接方案的有限列表，请参见图1-18中的UG381（并注意此列表并非包罗万象 - 例如，它不包括单端串联端接或并联端接到GND）。
为什么PlanAhead会自动插入外部终端方案呢？
通过UG632（我刚刚做的第一次），PlanAhead具有“同时切换噪声分析”功能，描述如下：
PlanAhead工具提供与不同设备的I / O相关的开关噪声水平的分析。
可以通过单击Flow Navigator中的“运行噪声分析”命令或从主菜单中的“工具”>“运行噪声分析”命令来访问此分析。
根据设计所针对的Xilinx器件，PlanAhead工具执行同步开关噪声（SSN）或同步开关输出（SSO）分析。
在提供噪声分析的过程中，PlanAhead对外部信号终止做出了一些假设，如下所述（添加了一些突出显示）：
片外终端 - 片外终端字段自动填充每个I / O标准的默认终端（如果存在）。
例如，对于LVTTL（2mA，4mA，6mA和8mA），不假设终止。
然而，对于LVTTL（在12mA，16mA和24mA），假设向VTT的50欧姆的远端并联终端。
由于这种终止，与2mA至8mA相比，驱动强度为12mA或更高的信号的可用噪声容限较小。
Virtex-4，Virtex-5，Virtex-6，Spartan-6和所有Xilinx 7系列FPGA器件都使用此假设。
显示无或预期或定义的片外终止样式的简短描述;
例如，FP_VTT_50描述了VTT端接类型的远端并行50Ω端接。
终端样式的完整列表可在附录E，其他资源中引用的特定于设备的SelectIO™资源用户指南中找到
要更改设置，请使用以下任一方法：
导入CSV格式文件中描述的CSV文件导入功能。
I / O端口表中的下拉选择。
从Kiran的原始帖子来看，他似乎试图超越假设的PlanAhead默认值，但没有成功。
此外，SSN分析可能对Kiran的设计非常有用和有趣（16位并行输出总线，具有高驱动电流）。
Kiran可能需要打开一个Webcase来弄清楚如何使用PlanAhead的噪声分析工具和正确的信号终止值。
如果无法指定正确的信号终止值，则Webcase对于提交PlanAhead软件错误报告非常有用。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
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以下为原文

Stephen is correct, I was mistaken. FP_VTT_50refers to externaltermination, not internaltermination. In other words, the presence or absence of FP_VTT_50termination attribute does not affect the FPGA output buffer.

As Stephen accurately explained, the need for internal (or external) termination depends on your application. If termination is needed, the type of termination also depends on your application. See UG381 Figure 1-18 for a limitedlist of some common termination schemes ( and note that this list is not all-inclusive -- it does not include single-ended series termination or parallel termination to GND, for example).

Why does PlanAhead bother with auto-insertion of external termination schemes? Looking through UG632 (which I just did for the first time), PlanAhead has a "Simultaneous Switching Noise Analysis" feature, described as follows:

The PlanAhead tool provides analysis of the switching noise levels associated with the I/O of different devices. This analysis can be accessed by clicking theRun Noise Analysiscommand from Flow Navigator or from theTools > Run Noise Analysiscommand from the main menu. Depending on the Xilinx device targeted by the design, the PlanAhead tool performs either a Simultaneous Switching Noise(SSN)or a Simultaneous Switching Output (SSO) analysis.

In the course of providing noise analysis, PlanAhead makes some assumptions with respect to external signal termination, described as follows (with some highlighting added):

Off-Chip Termination— The Off-Chip Termination field automatically populates with the default terminations for each I/O standard, if one exists. For example, for LVTTL (at 2mA, 4mA, 6mA, and 8mA) no termination is assumed.However, for LVTTL (at 12mA, 16mA, and 24mA) a far-end parallel termination of 50 Ohms to VTT is assumed.As a result of this termination, the available noise margin is less for signals with drive strength of 12mA, or more, when compared to 2mA to 8mA.

Virtex-4, Virtex-5,Virtex-6, Spartan-6, and all Xilinx 7 series FPGA devices use this assumption.

Displays eitherNoneor a short description of the expected or defined off-chip termination style; for example, FP_VTT_50 describes aFar-end Parallel 50 Ω termination to VTTtermination style.

The full list of termination styles is available in the device-specific SelectIO™ Resources User Guide, cited in Appendix E, Additional Resources

To change the settings, use either:

• The CSV file import feature described in Importing a CSV Format File.
  
• The pulldown selection in the I/O Ports table.
  

From Kiran's original post, it seems that he tried to over-ride the assumed PlanAhead default, without success. Furthermore, it is possible that SSN analysis may be very useful and interesting to Kiran's design (a 16bit parallel output bus, with high drive current).

Kiran may need to open a webcase to figure out how to use PlanAhead's noise analysis tool with the correct signal termination values. If the correct signal termination value cannot be specified, then the webcase will be useful for submitting the PlanAhead software bug report.

-- Bob Elkind
SIGNATURE:
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Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

我们在本讨论中提到了UG381（特别是图1-18，外部终端）。
我们在这次讨论中提到过UG632（特别是SSN分析）。
包含图1-18的UG381部分具有误导性和混淆性。
请允许我详细说明，首先摘自UG381 v1.4第33页（突出显示已添加）：
I / O终止技术
沿着导线的电信号的延迟由信号行进短距离时的上升和下降时间决定。
传输线延迟随电感和电容而变化。
精心设计的电路板可能会出现每英寸约180 ps的延迟。
对于快速（1.5 ns）的上升和下降时间，传输线效应或反射通常从1.5英寸开始。
传输线阻抗的不良（或不存在）终止或变化会导致这些反射，并且可能在较长的迹线中引起额外的延迟。
随着系统速度的不断提高，I / O延迟的影响可能成为限制因素，因此传输线终端变得越来越重要。
各种终端技术减少了传输线效应的影响。
输出终止技术可包括以下内容：
•无•串联•并联（分流）•串联和并联（串联 - 分流）•串联和差动
输入终止技术包括以下内容：
•无•并联（分流）•差分
图1-18中的终端方案说明了表1-3中列出的每种I / O标准的终止示例。
注释：
本摘录中的最后一句暗示图1-18是（或多或少）包含终止示例的全包列表
串联终端不包括在图1-18中
串联终端不包括在图1-18中
图1-18中未包括并行端接（至GND）
结论：图1-18并非包罗万象。
如果图1-18中的UG381的终止方案列表不是可用的SelectIO选项列表，则可能会问：该列表的目的是什么？
基于搜索此线程的有限文档，我可以设计的列表唯一合理的目的是：UG632中描述的PlanAhead SSN分析的电路模型列表。
遗憾的是，在UG381的I / O端接技术部分中没有提到UG632或SSN分析，图1-18所示。
PlanAhead和同时切换输出都在I / O端接技术部分之前的部分中提到，但是一个部分不是另一部分的一部分，两个部分也不是彼此参考。
简而言之，没有提到如何或为何或在何处应用图1-18中的信息。
如果SSN分析确实是图1-18中UG381的真正预期目的，那么省略这个上下文信息就有点自我挫败了。
更新：为了创建一个CR（文档更新请求）来整理UG632，我打开了一个webcase。
我无法想象这将被视为高优先级问题，但它会将更新放入文档更新队列中。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
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不要在多个论坛上发布相同的问题。
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以下为原文

We've mentioned UG381 (specifically Figure 1-18, external terminations) in this discussion.
We've mentioned UG632 (specifically SSN analysis) in this discussion.

The section of UG381 which includes Figure 1-18 is misleading and confusing. Permit me to elaborate, begining with an excerpt from UG381 v1.4 page 33 (highlighting added):

I/O Termination Techniques

The delay of an electrical signal along a wire is dominated by the rise and fall times when the signal travels a short distance. Transmission line delays vary with inductance and capacitance. A well-designed board can experience delays of approximately 180 ps per inch.

Transmission line effects, or reflections, typically start at 1.5 inches for fast (1.5 ns) rise and fall times. Poor (or non-existent) termination or changes in the transmission line impedance cause these reflections and can cause additional delay in longer traces. As system speeds continue to increase, the effect of I/O delays can become a limiting factor, and therefore transmission line termination becomes increasingly more important. A variety of termination techniques reduce the impact of transmission line effects. Output termination techniques can include the following:

• None
• Series
• Parallel (Shunt)
• Series and parallel (Series-Shunt)
• Series and differential

Input termination techniques include the following:

• None
• Parallel (Shunt)
• Differential

The termination schemes in Figure 1-18 illustrate the termination examples for each of the I/O standards listed in Table 1-3.

Comments:

• The last sentence in this excerpt implies that Figure 1-18 is a (more or less) all-inclusive list of termination examples
  
• Series termination is not included in Figure 1-18
  
• Series-shunt termination is not included in Figure 1-18
  
• Parallel termination (to GND) is not included in Figure 1-18
  
• Conclusion: Figure 1-18 is not all-inclusive.
  

If the termination scheme list of UG381 Figure 1-18 is NOTa list of available SelectIO options, the question may be asked: what is the purpose of this list?Based on the limited document searching for this thread, the only plausible purpose of this list I can devise is: a list of circuit models for the PlanAhead SSN analysis described in UG632.

Unfortunately, there is no reference to either UG632or SSN analysisin the I/O Termination Techniquessection of UG381, in which Figure 1-18 is located. PlanAheadand simultaneously switching outputsare both mentioned in the section which precedes the I/O Termination Techniquessection, but one section is not part of the other section, nor are the two sections referenced to each other. In short, there is no mention of howor whyor whereto apply the information in Figure 1-18. If SSN analysis is indeed the true intended purpose of UG381 Figure 1-18, then it is somewhat self-defeating to omit this context information.

UPDATE:I've opened a webcase in the interest of creating a CR (document update request) to tidy up UG632. I cannot imagine this will be considered a high-priority issue, but it will put the update into the document update queue.

-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

哈洛斯蒂芬＆amp;
鲍勃，
非常感谢你的精心回应。
我将进行SSN分析，还需要阅读PlanAhead用户指南（UG 632）。
@Bob：感谢您打开webcase。
最好的祝福，
基兰



以下为原文

Hallo Stephen & Bob,

thanks a lot for your elaborate response.
I ll do the SSN Analysis and need to read also the PlanAhead user guide (UG 632).

@Bob: Thanks for opening the webcase.

Best Regards,
Kiran

嗨鲍勃。
是的，你是对的。
图1-18和表1-3专门添加，以帮助在PlanAhead中使用SSNanalysis工具。
该工具的局限性在于，每个可选择终止的I / O标准最多只能有一个终端。
希望在SelectIO用户指南中描述此可选终止。
该工具中有一些链接指向SelectIO用户指南，以描述终止的内容。
并非所有人都认为“NP_VTT_50_FP_VTT_50”指的是“接近并联50欧姆到VttandFar并行50欧姆到Vtt”。
因此表1-3是解码器，图1-18显示了原理图。
从您的webcase制作的CR没有任何建议，除了删除所有内容（这不是一个选项），添加指向未命名的电路板设计指南（这是没有用的），并添加说明
SSN预测器工具是PlanAhead的一部分（不适合，应该在UG632中）。
我认为本次讨论中最好的建议之一就是在UG381的I / O端接技术部分添加“UG632或SSN分析参考”。
这并没有进入提交的CR，但我会尽力帮助它在未来的更新中实现。
谢谢你的建议，
-Scott Schlachter
Xilinx硅应用



以下为原文

Hi Bob. Yes, you are correct. Figure 1-18 and Table 1-3 were added specifically to aid with use of the SSN analysis tool in PlanAhead. The tool was limited in that each I/O standard that had an option of having a termination, could only have at most, one termination. There was a desire to describe this optional termination in the SelectIO User Guide. There are links in the tool to the SelectIO User Guide to describe what the termination was. Not everyone is expected to conclude that "NP_VTT_50_FP_VTT_50" refers to "Near Parallel 50 Ohms to Vtt and Far Parallel 50 Ohms to Vtt". So Table 1-3 is the decoder, and Figure 1-18 shows the schematic. The CR that was made from your webcase didn't have any suggestions other than to remove everything (which is not an option), add pointers to an un-named circuit board design guide (which isn't helpful), and add descriptions for the SSN Predictor tool which is part of PlanAhead (which isn't appropriate, as that should be in UG632).

I think one of the best suggestions in this discussion is to add a "reference to either UG632or SSN analysisin the I/O Termination Techniquessection of UG381". That didn't make it into the CR that was filed, but I will try to help make it happen in a future update.

Thank you for your suggestions,
-Scott Schlachter
Xilinx Silicon Applications