spartn6如何才能与这种总线接口？

你问过几个技术问题。
我会试着总结一下。
对于听众，可以在此处找到TLK2211数据表。
我有点困惑，我应该如何捕获数据并同步到内部时钟？
您尚未提供描述内部时钟，指定内部时钟频率或指定TLK2211链路数据速率的任何详细信息。
这些是重要且有用的细节。
如果内部时钟可以跟上数据接收速率，典型的使用方法是具有独立（异步）输入和输出时钟的输入FIFO。
输入时钟来自TLK2211，输出时钟是FPGA的内部时钟。
如果您还不熟悉Spartan-6 FIFO，那么这是一个学习的好时机。
你有更具体的问题吗？
有没有办法将两个时钟合并为一个时钟并用这个时钟捕获数据？
这是一个由两部分组成的问题。
1.您可以使用差分接收器输入合并FPGA上的两个时钟，在这种情况下，必须正确缩放输入电平（在电路板上，使用电阻网络），以提供与之兼容的LVDS输入电平
Spartan-6接收器。
目前尚不清楚您需要合并来自TLK2211的两个时钟信号 - 您只能使用两个RBC时钟输入中的一个作为单端LVTTL输入。
这两个选项中的任何一个都应该可靠地工作。
2.使用Spartan-6 IDDR2模块以半速率时钟捕获双数据速率输入数据。
在HDL中没有用于推断IDDR2块的通用语法，您需要在源代码中显式实例化IDDR2原语。
这是一个讨论输入接口的线程，它在某些方面类似于TLK2211。
注意：强烈建议对FPGA和TLK2211之间的接口信号进行适当的信号终止。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

You have asked several technical questions. I'll try to summarise them.

For the listening audience, the TLK2211 datasheet may be found here.

I'm a little puzzled how should I capture the data and sync to the internal clock?

You have not provided any details describing the internal clock, specifying the internal clock frequency, or specifying the TLK2211 link data rate. These are important and useful details.

If the internal clock can keep up with the data receive rate, the typical approach to use is an input FIFO with separate (asynchronous) input and output clocks. The input clock is from the TLK2211, and the output clock is the FPGA's internal clock. If you are not already familiar with Spartan-6 FIFOs, this is a good time to learn.

Do you have more specific questions in mind ?

Is there any way to merge the two clock to a single clock and capture the data with this clock?

This is a two-part question.

1. You can merge the two clocks on the FPGA with the use of a differential receiver input, in which case the input levels must be scaled correctly (on the circuit board, with a resistor network) to provide LVDS input levels which are compatible with the Spartan-6 receiver. It is not clear that you need to merge the two clock signals from the TLK2211 -- you can use only one of the two RBC clock inputs, as a single-ended LVTTL input. Either of these two options should work reliably.

2. Use the Spartan-6 IDDR2 blocks for capturing dual data rate input data with a half-rate clock. There is no generic syntax for inferring IDDR2 blocks in HDL, you will need to explicitly instantiate the IDDR2 primitives in your source code.

Here is a thread discussing an input interface which is in some ways similar to the TLK2211.

NOTE: Proper signal termination isstrongly advisedfor interface signals between the FPGA and the TLK2211.

-- Bob Elkind
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嗨鲍勃，
谢谢你的指示。
TLK2211的时钟频率为125Mhz。
根据你的建议，我通过IDDR2捕获rxdata，RBC0 / 1作为clock0和clock1，并将捕获的数据Q1，Q0推送到async-fifo，RBC0作为wr_clk，目前的问题是IDDR2上的捕获数据Q0
/ Q1总是0（尽管在第一个开始时切换），可能是什么问题？
txdata可以完美地环回到rxdata，我可以从Chipscope波形中看到。
以下是CS截图。



以下为原文

Hi Bob,

Thanks for your directions.

The clock frequency to TLK2211 is 125Mhz.
According to your suggestion, I capture the rxdata via IDDR2 with RBC0/1 as the clock0 and clock1,and push the captured data Q1, Q0 to a async-fifo with RBC0 as the wr_clk, currently problem is that the captured data on IDDR2 Q0/Q1 are always 0s(though toggled at the first beginning), what's maybe the problem?
the txdata could be perfectly loopback to rxdata, which I can see from Chipscope waveform.
following is the CS screenshot.

当同步前的第一个开始Q0 / Q1不为0时，也会附加波形（因此txdata不等于rxdata）。
我将IN_TERM = UNTUNED_SPLIT_50添加到rxdata，似乎不起作用。
谢谢，
加斯。



以下为原文

also attach the waveform when Q0/Q1 are not 0s in the first beginning before sync(so the txdata doesn't equal to rxdata).
and I added IN_TERM=UNTUNED_SPLIT_50 to rxdata, it seems doesn't work.


Thanks,
gauz.

对不起，我的重置信号似乎有问题，它将输出数据重置为0。
无论如何，谢谢你！高兹



以下为原文

Sorry, it seems there is some problem in my reset signal, which reset the output data to 0s.

Thanks to you anyway!
Gauz