[问答]

怎么生成一个独立的PWM源

1207 PWM

问答对人有帮助，内容完整，我也想知道答案0 大家好，我正在尝试使用Spartan 3E入门套件（500K，fg320）进行PWM生成。我精通C语言，但对VHDL很新。我为每个CLK事件设置了一个计数器，然后拉下u / down所需的引脚来获得PWM。但我认为这是一种蹩脚的方法，因为我只是获得了另一个源生成的PWM并对其进行处理。我想要实现的是生成一个独立的PWM源，具有可调频率和占空比。如果“等待”语句可用于实现，那将是一个肮脏的解决方案，但事实并非如此。您认为我的方法应该是什么？您会建议使用哪本书/来源来更深入地了解这些内容？谢谢祝你今天愉快。以上来自于谷歌翻译以下为原文 Hi all, I am trying to experiment with PWM genera ting using a Spartan 3E Starter Kit (500K,fg320). I am fluent in C but new to VHDL. I put a counter for each CLK event and pull-u/down necessary pin to get the PWM.But I think this is a lame way to do it because I am just getting the PWM generated by another source and processing it. What I want to achieve is to generate an independent PWM source, with adjustable frequency and duty cycle. If "wait for" statement was available to implement, that would be a dirty solution but it isn't. What do you think my approach should be ? Which book/source would you recommend to get more insight on these ? Thank you Have a nice day. 0
2019-6-24 14:16:33　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × asd008 该类别下有 32 个回答。邀请回答 aaaa321 该类别下有 27 个回答。邀请回答 doublelove 该类别下有 26 个回答。邀请回答 vynywrwr 该类别下有 21 个回答。邀请回答 hgjhgd 该类别下有 19 个回答。邀请回答 bwerwer 该类别下有 18 个回答。邀请回答 hanyan533 该类别下有 18 个回答。邀请回答 Jaionm 该类别下有 18 个回答。邀请回答 wang2222222 该类别下有 17 个回答。邀请回答 handsomelchcpp 该类别下有 17 个回答。邀请回答 binro 该类别下有 16 个回答。邀请回答 ningee 该类别下有 16 个回答。邀请回答 wznnzw 该类别下有 15 个回答。邀请回答 myf888 该类别下有 15 个回答。邀请回答 zcy615 该类别下有 14 个回答。邀请回答 wanglinhua2627 该类别下有 14 个回答。邀请回答 guotong1984 该类别下有 14 个回答。邀请回答 yhxc 该类别下有 14 个回答。邀请回答 armortech 该类别下有 14 个回答。邀请回答 60user25 该类别下有 14 个回答。邀请回答举报李正茂相关推荐 • Nuvoton提供的BSP驱动器库设置两个独立的PWM输出时频率会相互影响？1126 • 怎么生成一个PWM电路？4660 • 请问STM32L452CEU3必须要提供4个独立的PWM信号吗？199 • 如何使用STM32CubeMX配置STM32L431RCT6产生PWM驱动无源蜂鸣器？1459 • 如何仅在一个引脚上生成pwm输出SCT0_OUT3？199 • 怎样去生成一个10ms周期的PWM波形呢1472 • 请问用一个Timer_A怎么生成２路以上的PWM波？1081 • 如何用一个定时器的四个通道独立地输出四路PWM脉冲？1851 • 在RTTstudio里怎么配置一个PWM的4个通道1018 • CH579的PWM4~PWM11可以独立设置不同频率，同时输出不同频率的PWM么？541 1个回答

答案对人有帮助，有参考价值0 嗨， “通过另一个源生成PWM并进行处理”是什么意思？你在谈论你正在计数的时钟信号吗？如果你能熟练使用C语言，你可能会使用微控制器进行背景操作。您是否曾在数据表中查找过这种器件的PWM发生器部分？猜猜是什么，它也使用CPU时钟来从中获取PWM信号。所有可编程的东西，如频率，PWM分辨率（步长）等总是来自一些主时钟。在FPGA中，主时钟可以是几百MHz。使用满量程8位分辨率（占空比0到100％，256步），您可以达到大约一兆赫兹的频率。这应该胜过嵌入在微控制器中的大多数PWM发生器。但是，为了使事情可调整，您需要设计一些开销并实现必要的逻辑以使调整值生效。或者，如果您不需要/想要在运行时更改设置，则需要了解如何以可配置的可重用方式编写HDL源。对于VHDL泛型可能很有用。因此，您只需编写一些PWM生成模块，并在您的顶层设计中通过泛型设置它 PWM信号有不同的应用。看看他的那个（http://www.fpga4fun.com/PWM_DAC.html）。方法略有不同，但很好地解释了。此外，您还可以在该网站上找到更多适合初学者的实用提示。 HDL只是帮助您创建事物的工具。但真正需要的是对数字系统及其设计的基本理解。有一个很好的综合 Eilert 以上来自于谷歌翻译以下为原文 Hi, What do you mean by "getting the PWM generated by another source and processing it"? Are you refering to the clock signal that you are counting? If you are fluent with C you probably have some backgrond using microcontrollers. Have you once looked up the PWM generator section of such a device in the datasheet? Guess what, it uses the CPUs clock too to derive the PWM signals from that. All the programmable stuff, like frequency, PWM resolution (step width) etc. are always derived from some main Clock. In an FPGA the Main clock can be of some hundred MHz. With a full scale 8 bit resolution (duty cycle 0 to 100% in 256 Steps) you can reach frequencys of about a megahertz. That should beat most PWM generators embedded in microcontrollers. However, in order to make things adjustable you need to design with some overhead and implement the neccessary logic for the adjustment values to take effect. Or, if you do not need/want to change the settings during runtime, you need to learn how to write HDL sources in a configurable reusable way. For VHDL generics can be useful. Thus you write some PWM generating module once and set it properties by the generics in your toplevel design There are different applications for PWM signals. Take a look at his one ( http://www.fpga4fun.com/PWM_DAC.html ). The approach is a little different but nicely explained. Also you will find many more practical hints for beginners on that website. HDLs are just a tool to help you create things. But what is really needed is a fundamental understanding of digital systems and their design. Have a nice synthesis Eilert

2019-6-24 14:24:42 评论举报陈舒斌