你好
我在Spartan 6 LX150T设计中使用DDR2控制器,并且正在努力解决时钟资源问题。
我发现DDR控制器在其memc1_infrastructure_inst模块中有一个BUFGCE组件,如下所示:
// BUFGCE U_BUFG_CLK1 //(// .O(mcb_drp_clk),//。I(mcb_drp_clk_bufg_in),//。(锁定)//);
此实现阻止我使用相邻的BUFG位置来实例化Chipscope。
我暂时删除了该组件并将其替换为BUFG,从而取消了此时钟的PLL_ADV锁定输出所提供的限定条件。
这允许我再次放置设计,现在可以继续测试。
我的问题是:有人知道这样做的任何不利影响吗?
我知道在启动期间会有一段时钟的不确定性,但我准备接受这个,只要这不会扰乱DDR操作。
问候
基思
以上来自于谷歌翻译
以下为原文
Hi
I am using a DDR2 controller in a Spartan 6 LX150T design and am struggling with clock resources. I have found that the DDR controller has a BUFGCE component within its memc1_infrastructure_inst module as follows:
// BUFGCE U_BUFG_CLK1
// (
// .O (mcb_drp_clk),
// .I (mcb_drp_clk_bufg_in),
// .CE (locked)
// );
This implementa
tion prevents me from using the adjacent BUFG location for the instantiation of Chipscope. I have temporarily removed this component and replaced it with a BUFG, thereby removing the qualification provided be the PLL_ADV locked output for this clock. This allows me to place the design again and testing can now continue.
My question is this: Is anyone aware of any adverse implications of doing this?
I understand that there will be a period of clock uncertainty during startup, but I am prepared to accept this provided this does not upset the DDR operation.
Regards
Keith
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