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我正在使用时钟向导从40MHz产生25MHz的频率。
现在我收到此错误： 错误：Xst：2035 - 端口有非法连接。 此端口连接到输入缓冲区和其他组件。输入缓冲区：节点端口（IBUFG）单元其他组件：节点端口（FDE）单元 节点端口（FDE）单位 。 。 。 等等 除了新创建的25MHz时钟，我还需要使用原来的40MHz。 我是否必须使用时钟向导创建*两个*输出时钟？ CLK40连接到GCLK0 以上来自于谷歌翻译 以下为原文 I'm using the clocking wizard to generate 25MHz out of 40MHz. Now I get this error: ERROR:Xst:2035 - Port Input Buffer: Port of node Other Components: Port Port . . . and so on Besides the newly created 25MHz clock I still need to use the original 40MHz. Do I have to create *two* output clocks with the clocking wizard? CLK40 is connected to GCLK0 
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3个回答
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问题是输入缓冲区......
进入FPGA的所有输入都需要通过输入缓冲区 - IBUF（或IBUFG）。 焊盘本身只能连接到输入缓冲器的I输入。 从那里，缓冲器的O输出可以驱动FPGA的内部资源。 如果您没有实例化输入缓冲区（我建议实例化它们），那么工具将为您推断出一个。 因此，如果您的设计的顶级端口连接到内部资源，则工具将为您推断缓冲区。 因此，看起来您可以在没有输入缓冲区的情况下使用顶级设计的输入端口。 使用时钟向导时，它会构建整个时钟系统。 由于您（可能）选择“单端时钟引脚”作为时钟源，因此向导构建了一个模块，其中包含IBUFG的显式实例化 - 它被称为“monitor / instCLK25MHz / clkin1_buf”。 由于它是显式实例化的，因此您不能再直接使用输入，让工具推断缓冲区（您只能有一个）。 有两种方法可以解决这个问题。 第一种是从时钟向导生成两个时钟。 完成此操作后，向导将生成所有连接和缓冲区，以使两个时钟在系统中可用。 这可能是最简单的，也可能不需要任何额外的资源（因为向导可能会生成40MHz时钟的副本以供反馈，但如果你不要求它就不会把它带出来）。 另一种方法是将IBUFG从时钟向导中生成核心。 将时钟源设置为“无缓冲”。 然后，在设计的顶层，明确实例化IBUFG。 此实例化IBUFG的输出现在可在您的设计中使用 - 您可以使用它来驱动时钟向导的CLK_IN1输入以及其他内部资源。 从那里，您可能需要使用BUFG将其置于全局缓冲区。 然而，当以这种方式完成时，25MHz和40MHz时钟之间没有已知的相位关系，并且40MHz时钟不适合捕获输入/产生输出，因为它没有被DCM / MMCM去偏斜。 Avrum 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 The problem is the input buffer... All inputs coming in to the FPGA need to go through an input buffer - an IBUF (or IBUFG). The pad itself is ONLY able to be connected to the I input of an input buffer. From there, the O output of the buffer can drive internal resources of the FPGA. If you don't instantiate an input buffer (and I recommend instantiating them) then the tools will infer one for you. So, if you have a top level port of your design that is connected to internal resource, the tools will infer the buffer for you. Because of this, it looks like you can use an input port of your top level design without an input buffer. When you use the clocking wizard, it builds the whole clocking system. Since you (presumably) selected "Single ended clock capable pin" as the clock source, the wizard built a module that includes the explicit instantiation of the IBUFG - it is called "monitor/instCLK25MHz/clkin1_buf". Since it is explicitly instantiated, you can no longer simply use the input directly, letting the tool infer the buffer (you can have only one). There are two ways around this. The first is to generate both clocks coming out of the clocking wizard. When done this way, the wizard will generate all the connections and buffers to have both clocks useable in the system. This is probably the easiest, and also probably doesn't cost any additional resources (since the wizard is probably generating a copy of the 40MHz clock for feedback, but just not bringing it out if you don't ask for it). The other way around this is to take the IBUFG out of the clock wizard generated core. Set the Clock source to "No Buffer" instead. Then, in the top level of your design, explicitly instantiate an IBUFG. The output of this instantiated IBUFG is now available in your design - you can use it to drive the CLK_IN1 input of the clock wizard as well as other internal resources. From there, you would probably need to put it on a global buffer using a BUFG. However, when done this way, there is no known phase relationship between the 25MHz and 40MHz clock, and the 40MHz clock is not suitable for capturing inputs/generating outputs due to the fact that it is not deskewed by a DCM/MMCM. Avrum View solution in original post |
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问题是输入缓冲区......
进入FPGA的所有输入都需要通过输入缓冲区 - IBUF（或IBUFG）。 焊盘本身只能连接到输入缓冲器的I输入。 从那里，缓冲器的O输出可以驱动FPGA的内部资源。 如果您没有实例化输入缓冲区（我建议实例化它们），那么工具将为您推断出一个。 因此，如果您的设计的顶级端口连接到内部资源，则工具将为您推断缓冲区。 因此，看起来您可以在没有输入缓冲区的情况下使用顶级设计的输入端口。 使用时钟向导时，它会构建整个时钟系统。 由于您（可能）选择“单端时钟引脚”作为时钟源，因此向导构建了一个模块，其中包含IBUFG的显式实例化 - 它被称为“monitor / instCLK25MHz / clkin1_buf”。 由于它是显式实例化的，因此您不能再直接使用输入，让工具推断缓冲区（您只能有一个）。 有两种方法可以解决这个问题。 第一种是从时钟向导生成两个时钟。 完成此操作后，向导将生成所有连接和缓冲区，以使两个时钟在系统中可用。 这可能是最简单的，也可能不需要任何额外的资源（因为向导可能会生成40MHz时钟的副本以供反馈，但如果你不要求它就不会把它带出来）。 另一种方法是将IBUFG从时钟向导中生成核心。 将时钟源设置为“无缓冲”。 然后，在设计的顶层，明确实例化IBUFG。 此实例化IBUFG的输出现在可在您的设计中使用 - 您可以使用它来驱动时钟向导的CLK_IN1输入以及其他内部资源。 从那里，您可能需要使用BUFG将其置于全局缓冲区。 然而，当以这种方式完成时，25MHz和40MHz时钟之间没有已知的相位关系，并且40MHz时钟不适合捕获输入/产生输出，因为它没有被DCM / MMCM去偏斜。 Avrum 以上来自于谷歌翻译 以下为原文 The problem is the input buffer... All inputs coming in to the FPGA need to go through an input buffer - an IBUF (or IBUFG). The pad itself is ONLY able to be connected to the I input of an input buffer. From there, the O output of the buffer can drive internal resources of the FPGA. If you don't instantiate an input buffer (and I recommend instantiating them) then the tools will infer one for you. So, if you have a top level port of your design that is connected to internal resource, the tools will infer the buffer for you. Because of this, it looks like you can use an input port of your top level design without an input buffer. When you use the clocking wizard, it builds the whole clocking system. Since you (presumably) selected "Single ended clock capable pin" as the clock source, the wizard built a module that includes the explicit instantiation of the IBUFG - it is called "monitor/instCLK25MHz/clkin1_buf". Since it is explicitly instantiated, you can no longer simply use the input directly, letting the tool infer the buffer (you can have only one). There are two ways around this. The first is to generate both clocks coming out of the clocking wizard. When done this way, the wizard will generate all the connections and buffers to have both clocks useable in the system. This is probably the easiest, and also probably doesn't cost any additional resources (since the wizard is probably generating a copy of the 40MHz clock for feedback, but just not bringing it out if you don't ask for it). The other way around this is to take the IBUFG out of the clock wizard generated core. Set the Clock source to "No Buffer" instead. Then, in the top level of your design, explicitly instantiate an IBUFG. The output of this instantiated IBUFG is now available in your design - you can use it to drive the CLK_IN1 input of the clock wizard as well as other internal resources. From there, you would probably need to put it on a global buffer using a BUFG. However, when done this way, there is no known phase relationship between the 25MHz and 40MHz clock, and the 40MHz clock is not suitable for capturing inputs/generating outputs due to the fact that it is not deskewed by a DCM/MMCM. Avrum |
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感谢您提供非常全面的回复。
编辑：我看到让向导完成所有工作的一个问题。 如果我应用RESET，40MHz也将是不可用的。 在我的情况下它不是一个问题:) 以上来自于谷歌翻译 以下为原文 Thank you for a very comprehensive response. Edit: I see one problem with letting the wizard do all the work. If I apply RESET, the 40MHz will also be unavaiable. In my case its not a problem :) |
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