完善资料让更多小伙伴认识你，还能领取20积分哦， 立即完善>
3天内不再提示
德赢Vwin官网
论坛|
_ * Nutshell中的边界扫描* _ ICT测试需要“测试访问”。
这是指设计到PCB中的测试点（通常是焊盘或过孔），探针可以连接到测试点以提供被测板和测试仪之间的电气连接。 该测试标准由一个公司联盟于1990年组建，主要是为了解决由于减小PCB尺寸和增加包装到产品中的功能而越来越缺乏PCB组件的测试访问。 IEEE 1149.1（也称为边界扫描）是一种测试标准，涉及设计有移位寄存器的器件，如图1所示。每个移位寄存器称为边界扫描单元。 这些边界扫描单元允许您控制和观察每个输入和输出引脚上发生的情况。 当这些单元连接在一起时，它们形成一个称为边界寄存器的数据寄存器链。 边界扫描设备中还有其他寄存器。 •指令寄存器解码指令位，允许器件执行各种功能。 •旁路寄存器提供一位路径，最小化扫描输入和扫描输出之间的距离。 •标识寄存器，称为IDCODE寄存器，用于标识设备和制造商。 •其他设计人员指定的数据寄存器通常执行内部测试功能。 边界扫描设备有一个专用端口，称为测试访问端口（TAP），它将输入信号路由到称为TAP控制器的控制器和寄存器单元。 TAP控制器是一个控制边界寄存器的16状态机器。 图中所示的TAP信号用于控制边界扫描设备。 它们包括以下内容：•测试数据输入（TDI）：测试数据和指令位的串行输入。 •测试数据输出（TDO）：测试数据的串行输出。 •测试时钟（TCK）：用于驱动器件的独立时钟。 •测试模式选择（TMS）：这提供了将TAP控制器从状态更改为状态所需的逻辑电平。 •测试复位（TRST）可选：此可选输入提供TAP控制器的异步初始化，从而导致设计中包含的其他测试逻辑的异步初始化。 边界扫描设备可以执行许多测试功能。 其中三个，EXTEST，SAMPLE / PRELOAD和BYPASS，对于每个边界扫描设备都是必需的。 对于其他测试功能，INTEST，RUNBIST，IDCODE，CLAMP，HIGHZ和USERCODE由IEEE 1149.1标准描述，但是是可选的。 制造商还可以添加其实施遵循IEEE标准的测试功能。 以上来自于谷歌翻译 以下为原文 _*Boundary Scan in a Nutshell*_ Testing at ICT requires “test access”. This refers to the testpoints (usually pads or vias) that are designed into the PCB, that probes can connect to in order to provide the electrical connectivity between the board-under-test and the tester. The test standard was formed by a consortium of companies in 1990 mainly to address the increasing lack of test access on PCB assemblies due to reducing PCB sizes and increasing functionalities being packed into the product. IEEE 1149.1 (also known as Boundary scan) is a test standard that involves devices designed with shift registers placed between each device pin and the internal logic as shown in Figure 1. Each shift register is called a boundary scan cell. These boundary scan cells allow you to control and observe what happens at each input and output pin. When these cells are connected together, they form a data register chain, called the Boundary Register. There are other registers within a boundary-scan device. • An Instruction Register decodes instruction bits that allow the device to perform various functions. • A Bypass Register provides a one-bit path that minimizes the distance between the scan input and the scan output. • An Identification Register, called the IDCODE Register, identifies the device and manufacturer. • Other designer-specified data registers typically perform internal test functions. Boundary scan devices have a dedicated port, called the Test Access Port (TAP), that routes input signals to a controller, called the TAP Controller, and the register cells. The TAP Controller is a 16-state machine that controls the Boundary Register. The TAP signals shown in the illustration are used to control the boundary scan device. They include the following: • Test Data In (TDI): The serial input for test data and instruction bits. • Test Data Out (TDO): The serial output for test data. • Test Clock (TCK): An independent clock used to drive the device. • Test Mode Select (TMS): This provides the logic levels needed to change the TAP Controller from state to state. • Test Reset (TRST) Optional: This optional input provides asynchronous initialization of the TAP Controller, which in turn causes asynchronous initialization of other test logic included in the design. Boundary scan devices can perform many test functions. Three of these, EXTEST, SAMPLE/PRELOAD, and BYPASS, are mandatory for every boundary-scan device. For other test functions, INTEST, RUNBIST, IDCODE, CLAMP, HIGHZ, and USERCODE, are described by the IEEE 1149.1 standard, but are optional. Manufacturers can also add test functions whose implementation is guided by the IEEE standard. 附件
0
|
|
相关推荐
5个回答
|
|
|
_ *什么是BSDL文件以及它在边界扫描中的重要性？* _ BSDL文件是边界扫描描述语言文件的首字母缩写，是超高速IC硬件描述语言（VHDL）的一个子集，用于描述
边界扫描器件封装，引脚描述和输入和输出引脚的边界扫描单元。 BSDL文件在生成边界扫描测试中非常重要。 没有BSDL文件，就不可能生成任何边界扫描测试。 以上来自于谷歌翻译 以下为原文 _*What is a BSDL file and how important is it in boundary scan?*_ A BSDL file, which is the acronym for Boundary Scan Description Language file, is a subset of Very High Speed IC Hardware Description Language (VHDL) that describes the boundary scan device package, pin description and boundary scan cell of the input and output pins. The BSDL file is very important in generating a boundary scan test. Without a BSDL file, it is impossible to generate any boundary scan test. 附件
|
|
|
|
|
|
_ *边界扫描DFT指南：规则＃1：测试访问端口（TAP）的上拉或下拉电阻* _ TCK，TMS，TDI，TDO和TRST引脚上拉或下拉非常重要
在边界扫描测试期间通过电阻器降低。 电阻器用于防止IC在边界扫描测试期间无意中进入边界扫描模式或改变状态。 在大多数情况下，IC内部设置了弱上拉和下拉，但建议采用外部上拉和下拉。 推荐的配置是使用1.2kΩ（典型值）电阻将TDI，TDO，TMS和TRST上拉至Vcc，并通过100Ω电阻将TCK下拉至地。 用户可以参考IC设计文档，了解IC Designer的推荐电阻值。 上拉或下拉电阻的值可能影响总功耗。 例如，较低的上拉或下拉电阻需要更强的外部驱动能力。 以上来自于谷歌翻译 以下为原文 _*Boundary Scan DFT Guidelines: Rule#1: Pull-up or Pull-down resistors for Test Access Port (TAP)*_ It is very important for the TCK, TMS, TDI, TDO and TRST pins to be pulled up or pulled down by resistors during a boundary scan test. The resistors are there to prevent the IC from inadvertently entering into boundary scan mode or changing of states during a boundary scan test. In most cases, there are weak pull-ups and pull-downs designed into the IC, but external pull-ups and pull-downs are recommended. The recommended configuration is to pull up TDI, TDO, TMS and TRST with a 1.2kΩ (typical) resistor to Vcc and pull down TCK with a 100Ω resistor to ground. Users may refer to the IC design document for recommended resistance values from the IC Designer. The values of the pull-up or pull-down resistors may impact the overall power consumption. For example, lower pull-up or pull-down resistances require stronger external driver capabilities. |
|
|
|
|
|
_ *边界扫描指南：规则＃2：链接边界扫描设备以获得更好的测试覆盖率并更容易调试* _将每个边界扫描IC的TAP连接到菊花链中，第一个IC的TDO连接到第二个ICI的TDI
IC，第二IC的TDO连接到第三IC的TDI，依此类推。 TMS和TCK端口都与并行运行的跟踪短路在一起。 将TDI引脚设计为远离TDO引脚非常重要，以避免两者之间可能发生短路。 对于长链，需要考虑TCK和TMS的扇出。 缓冲电路可以放置在链中以增强链中的信号。 链中IC的顺序主要取决于IC的位置。 在可能的情况下，在链的末端放置新的和未经验证的边界扫描IC。 这样，如果需要，可以容易地从链中移除这些部件。 通过将边界扫描IC链接在一起，它允许测试信号通过测试单元在边界扫描IC之间传递（参见图2中的（A））。 测试仪不需要直接从这些节点驱动或接收信号; 因此，不需要测试点。 以上来自于谷歌翻译 以下为原文 _*Boundary Scan Guidelines: Rule#2: Chaining up boundary scan devices for better test coverage and easier debug*_ Connect the TAP of each boundary scan IC into a daisy chain with the TDO of the first IC connecting to the TDI of the second IC, the TDO of the second IC connecting to the TDI of the third IC, and so on. The TMS and TCK ports are all shorted together with the traces running in parallel. It is important to design the TDI pin away from the TDO pin to avoid possible short circuit between the two. For long chains, the fan-out of the TCK and TMS need to be considered. Buffer circuitry could be placed within the chain to boost the signal across the chain. The order of the ICs within the chain is mostly determine by the location of the ICs. Where possible, place new and unverified boundary scan ICs at the ends of the chain. This is so that these components can be easily removed from the chain if necessary. By chaining the boundary scan ICs together, it allows test signals to be passed between boundary scan ICs via the test cells (See (A) in Fig2). The tester does not need to drive or receive signals directly from these nodes; therefore, test points are not required. 附件
|
|
|
|
|
|
_ *边界扫描指南：规则＃3：需要时测试访问* _由于边界扫描组件的功能由TAP控制，因此每个TAP引脚都必须分配一个测试点。
没有它，就不可能使用边界扫描来测试组件。 在可能的情况下，最好在边界扫描IC之间的TDI-TDO连接上分配探针（参见图3中的（B））。 这些探针可用于通过隔离难以从链中调试的IC来帮助改进调试过程。 对于边界扫描组件上的其他引脚，应至少分配一个测试点。 这是为了验证组件是否可以进入边界扫描模式并能够输出正确的信号（参见图3中的（C））。 对于某些边界扫描IC，需要激活多个引脚（少于五个引脚）以使IC进入边界扫描模式。 这些引脚称为符合标准的引脚，它们需要对每个引脚进行测试访问。 边界扫描标准包括将警告消息添加到边界扫描描述语言（BSDL）文件中的语法。 该消息可以警告用户需要使用合规性启用引脚进行边界扫描测试。 以上来自于谷歌翻译 以下为原文 _*Boundary Scan Guidelines: Rule#3: Test access where needed*_ Since the function of the boundary scan component is controlled by the TAP, it is critical that each TAP pin has a test point assigned. Without which, it is not possible to test the component using boundary scan. Where possible, it is good to assign probes on the TDI-TDO connections between the boundary scan ICs (See (B) in Fig3). These probes can be used to help improve the debug process by isolating the ICs that are difficult to debug from the chain. For the other pins on the boundary scan component, there should be at least one test point assigned. This is to validate that the component can be put into boundary scan mode and able to output correct signals (See (C) in Fig3). For certain boundary scan ICs, a number of pins (less than five pins) need to be activated in order to put the IC into boundary scan mode. These pins are called compliance-enable pins and they would require test access on each of them. The boundary scan standard includes syntax to add warning messages into the boundary scan description language (BSDL) file. The message could warn users of the need to use the compliance-enable pins for boundary scan testing. 附件
|
|
|
|
|
|
_ *边界扫描指南：规则＃4：在不同逻辑电平的IC之间使用电平移位器* _根据电路设计，可能存在具有不同逻辑电平的TAP的边界扫描IC，这些TAP必须在链中连接在一起。
需要将电平移位器添加到这些IC之间的链中以管理不同的逻辑电平。 以上来自于谷歌翻译 以下为原文 _*Boundary Scan Guidelines: Rule#4: Using level shifters between ICs of different logic levels*_ Depending on the circuit design, there may be boundary scan ICs with TAPs of different logic levels that have to be connected together in a chain. Level Shifters need to be added to the chain between these ICs to manage the different logic levels. 附件
|
|
|
|
|
只有小组成员才能发言，加入小组>>
1283 浏览 0 评论
2371 浏览 1 评论
2189 浏览 1 评论
2062 浏览 5 评论
2946 浏览 3 评论
1103浏览 1评论
关于Keysight x1149 Boundary Scan Analyzer
750浏览 0评论
N5230C用“CALC:MARK:BWID？”获取Bwid,Cent,Q,Loss失败，请问大佬们怎么解决呀
921浏览 0评论
1283浏览 0评论
/6 
关注我们的微信
下载发烧友APP
德赢Vwin官网 观察
版权所有 © 湖南华秋数字科技有限公司
德赢Vwin官网 （电路图） 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证：合字B2-20210191
工商网监
湘ICP备2023018690号
4050
评论
淘帖
2485
