在chipcope中的问题

无论您触发什么，ILA模块的时钟必须连续运行
ChipScope工作。
该时钟用于采样所有输入以及所需的状态逻辑
引起。
另一方面，将时钟用作触发器通常没有意义，因为那样做
一直都在......
- Gabor
- Gabor



以下为原文

Regardless of what you're triggering on, the clock of the ILA module must run continously for
ChipScope to work. This clock is used to sample all of the inputs and also for state logic required
to trigger.

On the other hand it generally doesn't make sense to use a clock as a trigger, since that would
be going all the time...

-- Gabor
-- Gabor

感谢您快速重播......好的>>但是我在其他设计中使用时钟作为triger并且它正常工作...在此设计中的另一件事我将triger更改为DIP开关并且出现同样的问题



以下为原文

Thank you for fast replay ......
Ok >> but I use the clock as triger in other design and it is work properly ... another things in this design i change the triger to DIP switch and the same problem occur

这是真正的问题。
ILA内核具有时钟输入。
它有什么联系？
它是一个自由运行的时钟吗？
一个按钮？
门控时钟？
没有？
报告的问题是时钟缓慢或停止。
这意味着时钟输入
ILA核心，而不是设计的任何其他时钟。
- Gabor
- Gabor



以下为原文

Here's the real question. The ILA core has a clock input. What is it connected to? Is it a free-running clock?
A push-button? A gated clock? Nothing?

The problem that was reported is that the clock is slow or stopped. This means the clock input
of the ILA core, not any other clock of the design.

-- Gabor
-- Gabor

系统的时钟连接到ILA内核的输入时钟



以下为原文

The clock of the system is connected to the ILA core's input clock

omar.zyad写道：系统的时钟连接到ILA核心的输入时钟
您是否已验证系统的时钟实际正在运行（例如，将计数器位附加到LED）？
- Gabor
- Gabor



以下为原文

omar.zyad wrote:
The clock of the system is connected to the ILA core's input clock

And have you verified that the clock of the system is actually running (attach a counter bit to an LED for instance)?

-- Gabor
-- Gabor

我使用LED来验证系统是否完成了工作，但是这个位没有亮起......另一件事......在映射这个错误时发生错误：放置：1136 - 这个设计包含一个全局缓冲实例，驱动网络，
，即驱动以下（前30个）非时钟加载引脚。
这不是Spartan-6中推荐的设计实践，因为全局布线的限制可能导致过度延迟，歪斜或不可路由的情况。
建议仅使用BUFG资源来驱动时钟负载。
如果您希望覆盖此建议，可以使用.ucf文件中的CLOCK_DEDICATED_ROUTE约束（如下所示）将此消息降级为警告并允许您的设计继续。
错误：打包：1654 - 时序驱动的放置阶段遇到错误。但是当我将下一个代码放入ucf文件时，映射成功完成“PIN”CLK_BUFGP / BUFG.O“CLOCK_DEDICATED_ROUTE = FALSE;”



以下为原文

i use LED to verify the system if it is work done but this bit is not illuminate ...
Another thing .... during mapping this error occurs
ERROR:Place:1136 - This design contains a global buffer instance,
, driving the net, , that is driving the following
(first 30) non-clock load pins.
< PIN: U_ila_pro_0/U0/I_TQ0.G_TW[0].U_TQ.D; >
This is not a recommended design practice in Spartan-6 due to limitations in
the global routing that may cause excessive delay, skew or unroutable
situations. It is recommended to only use a BUFG resource to drive clock
loads. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue.
< PIN "CLK_BUFGP/BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

but when I put the next code in ucf file the mapping successfully completed
"PIN "CLK_BUFGP/BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;"

确保您的系统时钟连接到ILA的时钟输入引脚 - 没有其他ILA输入！
国际法协会
不是为了看时钟而设计的。
请记住，ILA是一个同步状态机和一切
其中包括输入采样，在时钟边缘运行。
用自己采样时钟是没有意义的。
现在我建议在你的设计中添加一个计数器，将时钟分成你能做到的
在LED上看，比如说每秒4个周期或更少。
例如，如果您的时钟以50 MHz运行，则可以使用
一个25位计数器并将MSB运行到LED。
如果没有眨眼，你就会知道你想要做的任何事情
使用ChipScope无法正常工作。
- Gabor
- Gabor



以下为原文

Make sure your system clock is connected to the ILA's clock input pin - and no other ILA input! The ILA
is not designed to look at clocks. Remember that the ILA is a synchronous state machine and everything
in it, including input sampling, runs on the clock edge. It makes no sense to sample a clock with itself.

Now I would suggest adding a counter to your design to divide the clock down to something you could
see on an LED, say 4 cycles per second or less. For example if your clock is running at 50 MHz you could use
a 25-bit counter and run the MSB to an LED. If it's not blinking you already know that anything you try to
do with ChipScope won't work.

-- Gabor
-- Gabor

谢谢......我试着告诉你结果



以下为原文

Thank you ... I try that and tell you the result

你好omar ...尝试使用你的输出作为触发器，所以输出的任何变化都会在chipcope中触发...



以下为原文

hello omar ... try to used your outputs as a trigger so any change in your output will make a trigger in the chipscope ...

谢谢我使用数据作为触发器并发生了同样的错误



以下为原文

Thank You < neam >

I used the data as trigger and the same error has occur

你有没有证实你真的得到了一个时钟？
您发布的错误确实没有
取决于触发器，只取决于时钟。
- Gabor
- Gabor



以下为原文

Did you ever verify that you're really getting a clock? The error you posted really doesn't
depend on triggers, just the clock.

-- Gabor
-- Gabor

None


以下为原文

Hi gszakacs

I make a counter in my system that divide the clock 2 cycle per second and connect it to LED but the LED dose not illuminates ... The problem in the clocks of the system .... Because the system is work properly when I used the 27MHz oscillator and the data can be read from chipscope but when I used the 200MHz the problem occurs ....
I do not know why this happens???

Note : I used SPARTAN 6

omar.zyad写道：
HigszakacsI在我的系统中制作了一个计数器，它将时钟每秒分成2个周期并将其连接到LED，但LED不会亮起......系统时钟的问题....因为系统在我使用时正常工作
27MHz振荡器和数据可以从chipcope读取，但当我使用200MHz时出现问题....
我不知道为什么会发生这种情况???注意：我使用的是SPARTAN 6
你有兴趣检查时序分析结果吗？
您是否有兴趣更改时钟周期约束并在将时钟从27 MHz更改为200 MHz时重新运行工具？
----------------------------是的，我这样做是为了谋生。



以下为原文

omar.zyad wrote:
Hi gszakacs

I make a counter in my system that divide the clock 2 cycle per second and connect it to LED but the LED dose not illuminates ... The problem in the clocks of the system .... Because the system is work properly when I used the 27MHz oscillator and the data can be read from chipscope but when I used the 200MHz the problem occurs ....
I do not know why this happens???

Note : I used SPARTAN 6

Did you bother to check the timing analysis results?
Did you bother to change the period constraint on the clock and rerun the tools when changed the clock from 27 MHz to 200 MHz?
----------------------------Yes, I do this for a living.

是的是的



以下为原文

Yes
Yes

也许您可以告诉我们200 MHz的来源。
它是FPGA的另一个输入
或者你是从27 MHz振荡器产生的？
您提供的信息越多，
提供更好的帮助质量。
- Gabor
- Gabor



以下为原文

Maybe you could tell us where the 200 MHz comes from. Is it another input to the FPGA
or are you generating it from the 27 MHz oscillator? The more information you provide, the
better quality of help you'll receive.

-- Gabor
-- Gabor

我使用了套件本身的200 MHz ......目标套件有两个源振荡器，一个200 MHz，另一个27 MHz
如用户指南中的表所示，我使用ucf文件中的K15来计时200 MHz时的时钟
当使用27 MHz时，我在ucf文件中使用V10来计时



以下为原文

I used the 200 MHz from the kit itself .... The target kit has two source oscillator one 200 MHz and other 27 MHz

As shown in table that take from User guide , I used K15 in ucf file to clock when using 200 MHz


and I used V10 in ucf file to clock when using 27 MHz

200 MHz时钟是差分的。
这就是为什么表中列出了两个引脚以及为什么你这样做的原因
需要在你的设计中使用它们。
执行此操作的唯一方法是实例化输入
缓冲区（IBUFDS），您可以在库指南中找到它以及实例化模板
对于VHDL或Verilog。
您可以将IBUFDS的输出用作时钟，工具将自动生成
插入一个BUFG，或者你也可以实例化BUFG。
无论如何LVDS信号来自
200 MHz时钟源没有足够的电压摆幅可与任何单端工作
IO标准。
这就是你的时钟“慢或停止”的原因。
- Gabor
- Gabor



以下为原文

The 200 MHz clock is differential. That's why there are two pins listed in the table and why you
need to use bothof them in your design. The only way to do this is to instantiate the input
buffer (IBUFDS) which you can find in the libraries guide along with the instantiation templates
for VHDL or Verilog. You can use the output of the IBUFDS as a clock and the tools will automatically
insert a BUFG, or you can instantiate the BUFG as well. In any case the LVDS signal from the
200 MHz clock source does not have enough voltage swing to work with any single-ended
IO standard. That's why your clock was "slow or stopped."

-- Gabor
-- Gabor

谢谢gszakacs ....我不需要使用差分时钟，但我需要使用单相200 MHz ......我从你的答案中了解到我应该在ILA输入时钟中使用它之前缓冲时钟信号...
用于缓冲时钟的下一个实例化模板----------------------------------------
BUFG_inst：BUFG端口映射（O => O， - 1位输出：时钟缓冲输出I => I - 1位输入：时钟缓冲输入）;
-----------------------------------------我会尝试并告诉你结果
谢谢你



以下为原文

Thanks gszakacs ....

I am not to need to use differential clock but I need to use single phase 200 MHz ....
I understand from your answer that I should buffered the clock signal before using it in ILA input clock ...
The next instantiation template that used to buffer the clock
----------------------------------------
BUFG_inst : BUFG
port map (
O => O, -- 1-bit output: Clock buffer output
I => I -- 1-bit input: Clock buffer input
);
-----------------------------------------
I will try that and tell you the results
Thanks agin

>我不需要使用差分时钟，但我需要使用单相200 MHz ....
您在板上连接到FPGA的差分时钟源。
如果不使用差分输入缓冲器（IBUFDS），则时钟不会进入器件。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> I am not to need to use differential clock but I need to use single phase 200 MHz ....

You have a differention clock source on the board that is connected to the FPGA. If you do not use a differential input buffer (IBUFDS) the clock will not make it into the device.
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com