请问从DCM环回中删除BUFG的优点/缺点是什么？

Ĵ，
优点是你保存了一个BUFG。
缺点是输出不再与输入相位对齐+/- 100 ps。
它们可能在某些其他值内对齐，但我们不知道它是什么，因为每个互连路径都没有完美地表征和匹配，这与全局时钟网络的特征和匹配方式相同。
如果您依赖于+/- 100 ps的相位对齐，则不能再依赖于它（它可能是其他固定值，+ / - 其他值）。
如果它是一个内部时钟，并且对齐无关紧要，那么这很好（做）。
如果那个时钟域必须交叉到另一个（它确实很重要），人们仍然可以使用同步器，但仍然不使用BUFG。
Austin Lesea主要工程师Xilinx San Jose
在原帖中查看解决方案



以下为原文

j,

The advantage is that you save a BUFG.

The disadvantage is the the outputs are no longer phase aligned +/- 100 ps to the input. They may be aligned to within some other value, but we do not know what that is, as every interconnect path is not perfectly characterized and matched, the same way that the global clock network is characterized and matched.

If you are relying on phase alignment being +/- 100 ps, you can no longer rely on that (it may be some other fixed value, +/- someother value).

If it is an internal clock, and alignment doesn't matter, then this is just fine (to do). If that clock domain has to cross over to another (it does matter), one can still use synchronizers, and still not use the BUFG.
Austin Lesea
Principal Engineer
Xilinx San JoseView solution in original post

Ĵ，
优点是你保存了一个BUFG。
缺点是输出不再与输入相位对齐+/- 100 ps。
它们可能在某些其他值内对齐，但我们不知道它是什么，因为每个互连路径都没有完美地表征和匹配，这与全局时钟网络的特征和匹配方式相同。
如果您依赖于+/- 100 ps的相位对齐，则不能再依赖于它（它可能是其他固定值，+ / - 其他值）。
如果它是一个内部时钟，并且对齐无关紧要，那么这很好（做）。
如果那个时钟域必须交叉到另一个（它确实很重要），人们仍然可以使用同步器，但仍然不使用BUFG。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

j,

The advantage is that you save a BUFG.

The disadvantage is the the outputs are no longer phase aligned +/- 100 ps to the input. They may be aligned to within some other value, but we do not know what that is, as every interconnect path is not perfectly characterized and matched, the same way that the global clock network is characterized and matched.

If you are relying on phase alignment being +/- 100 ps, you can no longer rely on that (it may be some other fixed value, +/- someother value).

If it is an internal clock, and alignment doesn't matter, then this is just fine (to do). If that clock domain has to cross over to another (it does matter), one can still use synchronizers, and still not use the BUFG.
Austin Lesea
Principal Engineer
Xilinx San Jose

cvtabc写道：
你好奥斯汀
在该帖子的原始问题中，提到了由ISE“自动”将BUFG元素插入到DCM的时钟反馈路径CKL0-> CLKFB中。
我的设计中没有发现这种情况。
我使用的是Spartan 3和ISE 9.1。
我必须在反馈路径中插入一个BUFG。
如果我不这样做，从CLK0到DCM的CLKFB引脚的物理路由进入大腿环路，穿过DCM周围的交换结构/元件。
看附图。
它以红色显示路径。
当我插入BUFG时，反馈路径被强制通过全局clcok网络。
你能否对此发表评论？
也许我有一些选项没有设置自动BUFG插入？
对于支持这些设备的ISE工具的所有版本，我使用Spartan 3设备（所有这些设备，从原来的3，3E，3A和3AN）的经验是，如果您使用DCM，则必须实例化所有设备
必要的BUFG和LOC全部。
没有任何推断，即使文档清楚GCLK引脚与特定的BUFG和DCM有什么联系，但这些工具实际上找不到它们实在太愚蠢了。
什么是bset练习..即使您不关心外部clcok与派生内部时钟之间的相位关系，您是否应该通过全局时钟网络进行时钟反馈？
我认为这些工具不会让你将DCM反馈输入连接到除BUFG输出之外的任何东西，即全局时钟网。
----------------------------是的，我这样做是为了谋生。



以下为原文

cvtabc wrote:
Hello Austin

In the original question of this post it was mentioned that a BUFG element is "automatically" inserted by ISE into the clock feedback path CKL0->CLKFB of a DCM.

I don't find this to be the case in my design. I use a Spartan 3 and ISE 9.1. I have to explisitly insert a BUFG in the feedback path. If I don't do it the physical routing from CLK0 to my CLKFB pin of the DCM goes in a thigh loop through the switching fabric/elements surrounding the DCM. Look at the attached picture. It shows the path in red.

When I insert a BUFG the feedback path is forced via the global clcok network.

Can you comment on this please. Maybe I have some option not set to do automatic BUFG insertion?

My experience with the Spartan 3 devices (all of them, from the original 3, the 3E, the 3A and 3AN), for all versions of the ISE tools that support those devices, is that if you use a DCM, you must instantiate all of the necessary BUFGs and LOC all of them. Nothing is inferred, and even though the docs are clear on what GCLK pins talk to what specific BUFGs and DCMs, the tools are simply too stupid to actually locate them properly.

What is the bset practice.. should you have clock feedback go through the global clock network even if you are not concerned about phase relationship between your external clcok and the derived internal clock?

I don't think the tools will let you connect the DCM feedback input to anything but a BUFG output, that is, a global clock net.
----------------------------Yes, I do this for a living.