我真的不明白为什么会这样,有人可以赐教:
我创建了一个独立时钟的FIFO。
写入侧使用外部时钟。
我使用PLL(频率因子为1:1,只是为了消除抖动)来产生读时钟。
现在我得到了非常好的保持时间。
PAR给了我
警告:路由:522 - 在10个连接中检测到异常高的保持时间违规。
路由器将继续并尝试修复它
这是有问题的代码:
wire pll_clkout0,pll_clkfbout;
PLL_BASE#(。BANDWIDTH(“LOW”),//设置为“LOW”以获得更好的抖动滤波器.CLK_FEEDBACK(“CLKFBOUT”),. COMPENSENS(“INTERNAL”),. DIVCLK_DIVIDE(1),. CLKFBOUT_MULT(6),
// PLL在891 MHz .CLKFBOUT_PHASE(0.000),. CLKOUT0_DIVIDE(6),// fout = fin .CLKOUT0_PHASE(0.000),. CLKOUT0_DUTY_CYCLE(0.500),. REF_JITTER(0.010))hi_jitter_pll(.RST(rst),/
/输入时钟控制.CLKIN(hi_pclk),. CLKFBIN(pll_clkfbout),. CLKFBOUT(pll_clkfbout),. CLKOUT0(pll_clkout0),. LOCKED(pll_locked));
BUFG clkout0_buf(.I(pll_clkout0),. O(hi_pclk_g));
//在FIFO的输入处注册@ @(posedge hi_pclk)开始hi_fifo_in结束// FIFO hi_fifo_51x16 hi_input_fifo(.rst(rst),//输入rst .wr_clk(hi_pclk),//输入wr_clk .wr_en(!hi_fifo_full),/
/ input wr_en .din(hi_fifo_in),//输入[50:0] din .full(hi_fifo_full),//输出满.rd_clk(hi_pclk_g),//输入rd_clk .rd_en(!hi_fifo_empty),//输入rd_en。
dout(hi_fifo_out),// output [50:0] dout .empty(hi_fifo_empty)//输出空);
//在FIFO的输出端注册@ @(posedge hi_pclk_g)start hdmi_in_vid hdmi_in_sync end
这是PAR所说的:
阶段7:0未布线;
实时:50秒警告:路由:522 - 在13个连接中检测到异常高的保持时间违规。路由器将继续并尝试修复它阶段9:0未布线;
(设置:4009,保持:109747,组件切换限制:0)hi_input_fifo / U0 / xst_fifo_generator / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / gsync_stage [1] .rd_stg_inst / D:CQ - > hi_input_fifo / U0
/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D:CX -3683 ...
FIFO不应该删除写入和读取端口之间的所有时序关系吗?
如果我添加一个
tiG约束,问题就会消失。
TIMESPEC TS_hi_fifo_tig =从“hi_pclk”到“hi_pclk_g”TIG;
Strangley足够了,即使通过TIG,应用于hi_pclk的PERIOD约束也会转移到hi_pclk_g。
TIG不应该导致hi_pclk_g完全不受约束吗?
谢谢,
布鲁诺
以上来自于谷歌翻译
以下为原文
I don't really understand why this happens, can someone please enlighten me:
I create a FIFO with independent clocks.
An external clock is used on the write side.
I use a PLL (with 1:1 frequency factor, just to remove jitter) to generate the read clock.
Now I get ENORMOUS hold times.
PAR gives me
WARNING:Route:522 - Unusually high hold time violation detected among 10 connections. The router will continue and try to fix it
Here is the code in question:
wire pll_clkout0, pll_clkfbout;
PLL_BASE
#(.BANDWIDTH ("LOW"), // Set to "LOW" for better jitter filter
.CLK_FEEDBACK ("CLKFBOUT"),
.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (6), // PLLat 891 MHz
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (6), // fout = fin
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.REF_JITTER (0.010))
hi_jitter_pll
(.RST (rst),
// Input clock control
.CLKIN (hi_pclk),
.CLKFBIN (pll_clkfbout),
.CLKFBOUT (pll_clkfbout),
.CLKOUT0 (pll_clkout0)
, .LOCKED (pll_locked)
);
BUFG clkout0_buf (.I(pll_clkout0), .O(hi_pclk_g));
// Register at inputof the FIFO
always @ (posedge hi_pclk) begin
hi_fifo_in <= { hdmi_iob_s_regs, hdmi_iob_p_regs } ;
end
// FIFO
hi_fifo_51x16 hi_input_fifo (
.rst(rst), // input rst
.wr_clk(hi_pclk), // input wr_clk
.wr_en(!hi_fifo_full), // input wr_en
.din(hi_fifo_in), // input [50 : 0] din
.full(hi_fifo_full), // output full
.rd_clk(hi_pclk_g), // input rd_clk
.rd_en(!hi_fifo_empty), // input rd_en
.dout(hi_fifo_out), // output [50 : 0] dout
.empty(hi_fifo_empty) // output empty
);
// Register at output of the FIFO
always @ (posedge hi_pclk_g) begin
hdmi_in_vid <= hi_fifo_out[47:0] ;
hdmi_in_sync <= hi_fifo_out[50:48] ;
end
And here is what PAR says:
Phase 7 : 0 unrouted; REAL time: 50 secs
WARNING:Route:522 - Unusually high hold time violation detected among 13 connections.The router will continue and try to fix it
Phase 9 : 0 unrouted; (Setup:4009, Hold:
109747, Component Switching Limit:0) hi_input_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<3>:CQ ->
hi_input_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<3>:CX -3683
...
Shouldn't the FIFO remove all timing relationships between the write and read ports?
If I add a TIG constraint the problem goeas away.
TIMESPEC TS_hi_fifo_tig = FROM "hi_pclk" TO "hi_pclk_g" TIG ;
Strangley enough, the PERIOD constraint applied to hi_pclk gets transfered to hi_pclk_g, even through the TIG.
Shouldn't the TIG cause hi_pclk_g to go totally unconstrained?
Thank you,
Bruno
0