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我正在运行Spartan 6 block ram的模拟。
时钟速度为100Mhz。 块ram的写作运作良好。 我可以在内存中看到数据。 但是当我读取数据时，输出有2个时钟的延迟。 在块ram用户guidt中，它只表示1个时钟延迟。 如果有人能帮忙看看，我将不胜感激。 我在这里附上了我的源代码和模拟快照。 源代码：解压后请打开项目文件：.. study par opcode opcode.xise。 屏幕简短说明：数据在地址0处为0x09，在地址1处为0x13，在地址2处为0xa，在地址0x3处为0x14。 从模拟开始，它具有2个时钟延迟，以便在上升时钟呈现地址后获得正确的数据输出。 提前致谢！ 方 study.zip 3795 KB 以上来自于谷歌翻译 以下为原文 I am running a simulation of Spartan 6 block ram. The clock speed is 100Mhz. The writing of block ram is working well. I can see the data in memory. But when I read the data the output has 2 clocks of latency. In block ram user guidt it says only 1 clock latency. I will appreciate if anyone can help to look at it. I attached my source code and simulation snapshot here. Source code: After unzip please open the project file located at: ..studyparopcodeopcode.xise. Screen short explanation: The data is 0x09 at address 0, and 0x13 at address 1, 0xa at address 2, 0x14 at address 0x3. From the simulation it has 2 clocks latency to get correct data out after presenting address at rising clock. Thanks in advance! Fang study.zip 3795 KB 
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另请注意，Spartan-6 Block RAM位于整个结构中的固定位置。
如果您的Block RAM阵列太大而无法放入单个Block RAM中，则共享信号无法避免额外的互连延迟。 对此的对策是生成地址的重复集（副本）并控制阵列中每个块RAM的信号。 这对你有意义吗，还是需要进一步阐述？ - 鲍勃埃尔金德 签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。 阅读手册或用户指南。 你读过手册了吗？ 你能找到手册吗？2。 搜索论坛（并搜索网页）以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题，开始新的主题！5。 学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息（请与网页，数据表链接）.7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章，那么我一无所获。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Note also that Spartan-6 block RAMs are in fixed locations throughout the fabric. If your block RAM array is too large to fit in a single block RAM, then additional interconnect delays are unavoidable for shared signals. The countermeasure for this is to generate duplicate sets (copies) of address and controls signals for each block RAM in the array. Does this make sense to you, or do you need further elaboration? -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.View solution in original post |
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嗨，
读取数据延迟取决于核心配置，如单个/独立时钟，也取决于read_enable断言时间。 我认为2个时钟是预期的行为，请通过各自核心版权的PG058的“Latency”部分 最新的Vivado PG http://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v8_2/pg058-blk-mem-gen.pdf 最新的ISE PG http://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v7_3/pg058-blk-mem-gen.pdf 如果您认为任何关于doc的核心行为不当请告诉我们 问候， Vanitha -------------------------------------------------- -------------------------------------------请在发布前进行谷歌搜索， 您可能会找到相关信息。请留下帖子 - “接受为解决方案”，如果提供的信息有用且回复，请给予赞誉 以上来自于谷歌翻译 以下为原文 Hi, Read data latency depends on core configuration like single/independent clocks and also on the read_enable assertion time. I think 2 clocks is expected behaviour, please go through "Latency" Section of PG058 of your respective core verison Latest Vivado PG http://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v8_2/pg058-blk-mem-gen.pdf Latest ISE PG http://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v7_3/pg058-blk-mem-gen.pdf If you think any mi***ehaviour of the core with respect to doc please let us know Regards, Vanitha --------------------------------------------------------------------------------------------- Please do google search before posting, you may find relavant information. Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented |
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嗨Vanitha，
感谢您的快速回复。 我读了延迟部分。 它表示如果有输出重定时器，它将增加一个额外的时钟周期延迟。 但在我的配置中，我没有选择输出寄存器。 我使用的是ISE 13.4，内存核心版本是V6.3。 请您打开我的项目文件并查看配置吗？ 我将非常感谢你的帮助！ 谢谢， 方 以上来自于谷歌翻译 以下为原文 Hi Vanitha, Thanks for your quick reply. I read the latency section. It says if there is output resigter it will add an additional clock cycle delay. But in my configuration I did not select output registers. I am using ISE 13.4 and memory core version is V6.3. Could you kindly please open my project file and have a look at the configuration? I will appreciate your great help! Thanks, Fang |
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看起来您正在运行路径后模拟，并且仅使用5 ns设置将输入应用于时钟。
您看到的额外周期可能是由于设计在这些条件下不符合时序的事实。 我看了一下行为模拟，看起来输出是在预期的时钟边缘（更快一个周期）。 - Gabor 以上来自于谷歌翻译 以下为原文 It looks like you're running a post-route simulation, and applying the input with only 5 ns setup to the clock. It's likely that the additional cycle you see is due to the fact that the design doesn't meet timing under these conditions. I looked at a behavioral simulation and it looks like the output comes at the expected clock edge (1 cycle sooner). -- Gabor |
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嗨Gabor，
感谢您的回复。 是的你是对的我正在进行路线后模拟。 我对行为模拟也没有问题。 我认为后期模拟比关于时间的行为模拟更准确。 我的应用是100Mhz时钟，当地址在周期n上计时时数据在周期n + 1输出。 在spartan 6数据表中，它表示块ram最大频率为280Mhz。 所以我尝试运行我的逻辑生成地址100Mhz，而块ram运行在200Mhz但我从来没有得到正确的数据。 似乎200Mhz对于滑块来说太快了。 关于申请的任何建议？ 谢谢 以上来自于谷歌翻译 以下为原文 Hi Gabor, Thanks for your reply. Yes you are correct I am doing post route simulation. I have no problem on behavior simulation too. I think post route simulation will be more accurate than behavior simulation regarding the timing. My application is with 100Mhz clock when address is clocked on cycle n the data is out at cycle n+1. In spartan 6 datasheet it says block ram max frequency is 280Mhz. So I tried to run my logic generating address with 100Mhz while block ram running at 200Mhz but I never got correct data. It seems 200Mhz is too fast for block ram. Any advice about the application? Thanks |
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在spartan 6数据表中，它表示块ram最大频率为280Mhz。
所以我尝试运行我的逻辑生成地址100Mhz，而块ram运行在200Mhz但我从来没有得到正确的数据。 似乎200Mhz对于滑块来说太快了。 如果您可以使用所需的设置时间（相对于时钟）向块RAM提供数据，命令和地址，那么Block RAM确实可以在高达280MHz的频率下运行。 事实上，Xilinx保证了这一点。 重新审视驱动Block RAM的逻辑的时序路径。 请参见Block RAM输入的逻辑路径的延迟组件。 它们包括逻辑（LUT）延迟，寄存器延迟（Q时钟，时钟数据设置）和互连延迟。 您可以通过合并逻辑电平和减少互连长度来改善时序余量。 如果你聪明而谨慎，那么在100MHz时操作Spartan-6 Block RAM并获得充足的时序余量应该没有问题。 在200MHz下工作将需要更多的关注。 - 鲍勃埃尔金德 签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。 阅读手册或用户指南。 你读过手册了吗？ 你能找到手册吗？2。 搜索论坛（并搜索网页）以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题，开始新的主题！5。 学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息（请与网页，数据表链接）.7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章，那么我一无所获。 以上来自于谷歌翻译 以下为原文 In spartan 6 datasheet it says block ram max frequency is 280Mhz. So I tried to run my logic generating address with 100Mhz while block ram running at 200Mhz but I never got correct data. It seems 200Mhz is too fast for block ram. If you can deliver data, commands, and addresses to the block RAM with required setup time (with respect to the clock), then the block RAM will indeed operate at up to 280MHz. Xilinx guarantees this, in fact. Revisit your timing paths for logic which drives the block RAM. See the delay components of the logic paths to the block RAM inputs. They will consist of logic (LUT) delay, register delays (clock to Q, data setup to clock), and interconnect delays. You can improve timing margins by consolidating logic levels and reducing interconnect lengths. If you are clever and prudent, you should have no problem operating Spartan-6 block RAM at 100MHz with ample timing margin. Operating at 200MHz will require much more care. -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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另请注意，Spartan-6 Block RAM位于整个结构中的固定位置。
如果您的Block RAM阵列太大而无法放入单个Block RAM中，则共享信号无法避免额外的互连延迟。 对此的对策是生成地址的重复集（副本）并控制阵列中每个块RAM的信号。 这对你有意义吗，还是需要进一步阐述？ - 鲍勃埃尔金德 签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。 阅读手册或用户指南。 你读过手册了吗？ 你能找到手册吗？2。 搜索论坛（并搜索网页）以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题，开始新的主题！5。 学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息（请与网页，数据表链接）.7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章，那么我一无所获。 以上来自于谷歌翻译 以下为原文 Note also that Spartan-6 block RAMs are in fixed locations throughout the fabric. If your block RAM array is too large to fit in a single block RAM, then additional interconnect delays are unavoidable for shared signals. The countermeasure for this is to generate duplicate sets (copies) of address and controls signals for each block RAM in the array. Does this make sense to you, or do you need further elaboration? -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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嗨鲍勃，
感谢您的回复。 我需要大块滑块，它是4096 * 64bits。 我也找到了你在这里提到的内容。 当深度和宽度较小时，模拟显示出良好的结果。 但是一旦我增加深度或宽度就会有问题。 现在我试图以50Mhz运行它，但使用真正的端口块ram，因此可以用一个周期（50Mhz）读取两个数据。 它似乎运行100Mhz但它会使逻辑更复杂。 方 以上来自于谷歌翻译 以下为原文 Hi Bob, Thanks for your reply. I need big block ram which is 4096 * 64bits. I also found what you mentioned here. When the depth and width are small the simulation shows good result. But once I increase depth or width it will have problem. Now I am trying to run it at 50Mhz but using true port block ram thus two data could be read with one cycle (50Mhz). It seems it is running 100Mhz but it will make the logic more complicated. Fang |
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你在运行地点和路线时是否使用时间限制？
------您是否尝试在Google中输入问题？ 如果没有，你应该在发布之前。太多结果？ 尝试添加网站：www.xilinx.com 以上来自于谷歌翻译 以下为原文 Are you using timing constraints when running place and route?------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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fanghuagang78写道：
嗨Gabor， 感谢您的回复。 是的你是对的我正在进行路线后模拟。 我对行为模拟也没有问题。 我认为后期模拟比关于时间的行为模拟更准确。 我的应用是100Mhz时钟，当地址在周期n上计时时数据在周期n + 1输出。 在spartan 6数据表中，它表示块ram最大频率为280Mhz。 所以我尝试运行我的逻辑生成地址100Mhz，而块ram运行在200Mhz但我从来没有得到正确的数据。 似乎200Mhz对于滑块来说太快了。 关于申请的任何建议？ 谢谢 您在后期路线模拟中运行的设计实际上是顶层设计（最终设计中包含所有功能）吗？ 如果没有，运行后P＆amp; R模拟没有价值，因为它不会显示实际系统中的实际时间。 实际上它会非常悲观，因为IO端口将被添加到被测模块中，如果这些端口需要快速工作，额外的输入或输出缓冲延迟将导致您看到的那种时序问题。 - Gabor 以上来自于谷歌翻译 以下为原文 fanghuagang78 wrote:Is the design you're running in post route simulation actually the top-level design (final design with all functions in it)? If not, running post P&R simulation is of no value, since it won't show you the actual timing in the real system. In fact it will tend to be very pessimistic since IO ports will be added to the module under test, and if these ports need to work fast the additional input or output buffer delays will cause the sort of timing problems you're seeing. -- Gabor |
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