我有兴趣在IDDR2和ODDR2前面使用一个IODELAY2作为Spartan 6上60MHz DDR接口的一部分。但我对一些属性和端口感到困惑。
对于IDELAY_TYPE:不管您将其设置为什么,DEFAULT强制IDELAY_VALUE为0的FIXED和DEFAULT之间的区别是什么?
如果我想能够使用inc端口,我认为这会迫使我进入VARIABLE,对吧?
SIM_TAP_DELAY有哪些单位?
它表示你可以将它设置在20到100之间。这是否意味着每个tap设置为(SIM_TAP_DELAY)ps?
或者是其他东西?
即如果你将IDELAY_VALUE设置为10而SIM_TAP_DELAY设置为20,你的总延迟将是10 * 20ps = 200ps?
对于DATA_RATE:我假设我想把这个设置为DDR,因为我通过这个做DDR数据?
UG381中的描述没有明确说明这一点,但我正在做出这样的假设。
对于CLK,IOCLK0和IOCLK1:我不明白这些之间的差异,以及我应该对它们做些什么。
我知道如果我想使用变量idelay_type,我想要一个时钟进入系统 - 但我不知道它应该进入哪个端口。
此外,相邻IODELAY2块的延迟应该如何匹配?
我的假设是他们会非常相似。
最后,有什么方法可以在我的时钟低于Fmincal(188MHz)时进行校准吗?
我假设没有,但我想我应该问。
任何人都可以对这些事情有所了解吗?
谢谢!
以上来自于谷歌翻译
以下为原文
I am interested in using an IODELAY2 in front of an IDDR2 and ODDR2 as part of a 60MHz DDR interface on a Spartan 6. I'm confused regarding some of the attributes and ports, however.
For IDELAY_TYPE: is the difference between FIXED and DEFAULT that DEFAULT forces IDELAY_VALUE to 0, regardless of what you set it to? If I want to be able to use the inc port, I think that forces me into VARIABLE though, right?
What are the units of SIM_TAP_DELAY? It says you can set it between 20 and 100. Does that mean that each tap is set to (SIM_TAP_DELAY) ps? or something else? ie if you set IDELAY_VALUE to 10 and SIM_TAP_DELAY to 20, your total delay would be 10*20ps=200ps?
For DATA_RATE: I'm assuming I want this set to DDR, since I'm doing DDR data through this? The descrip
tion in UG381 doesn't explicitly say this, but I'm making that assumption.
For CLK, IOCLK0, and IOCLK1: I do not understand the difference between these, and what I'm supposed to do with them. I understand that if I want use of the variable idelay_type, I want a clock going into the system - but I don't know which port it should go into.
Further, how matched should the delays in adjacent IODELAY2 blocks be? My assumption is that they'll be very similar.
Finally, is there any way to calibrate when my clock is below Fmincal (188MHz)? I am assuming no, but thought I should ask.
Can anybody shed some light on these things?
Thank you!
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