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大家好，
我在spartan-6 FPGA（XC6SLX9TQ144）板上遇到了问题。 我发现我的FPGA的所有io引脚在配置之前都处于高位状态。但是我需要它们低。 我不知道究竟是什么原因。 我对HSWAPEN引脚有疑问。 我拉下这个针。 问候， Shahul 以上来自于谷歌翻译 以下为原文 Hi all, i have a problem in spartan-6 FPGA(XC6SLX9TQ144) board. i found that all io pin of my FPGA are in high sate before configuration.But i need them to be low. i don't know what is the exact reason. i doubt on HSWAPEN pin. i pull down this pin. Regards, Shahul 
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以上来自于谷歌翻译 以下为原文 From UG380 section titled FPGA I/O Pin Settings During Configuration: ... However, all user I/O pins have optional pull-up resistors that can be enabled during the configuration process. During configuration, a single control line determines whether the pull-up resistors are enabled or disabled. The pin name is HSWAPEN Note that there is no provision for pull-down resistors during configuration, only pull-up resistors (disabled by HSWAPEN input). If you want User IOs to be LOW (instead of HIGH or Z) during configuration, you must provide external pulldown circuits. Driving HSWAPEN input pin LOW will enable the internal pull-up resistors on all User IO pins until configuration is completed. -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.View solution in original post |
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从配置期间标题为FPGA I / O引脚设置的UG380部分：
...但是，所有用户I / O引脚都有可选的上拉电阻，可在配置过程中启用。 在配置期间，单个控制线确定是启用还是禁用上拉电阻。 引脚名称为HSWAPEN 请注意，配置期间不提供下拉电阻，仅提供上拉电阻（通过HSWAPEN输入禁用）。 如果您希望在配置期间用户IO为低（而不是HIGH或Z），则必须提供外部下拉电路。 将HSWAPEN输入引脚驱动为低电平将使能所有用户IO引脚上的内部上拉电阻，直到配置完成。 - 鲍勃埃尔金德 签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。 阅读手册或用户指南。 你读过手册了吗？ 你能找到手册吗？2。 搜索论坛（并搜索网页）以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题，开始新的主题！5。 学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息（请与网页，数据表链接）.7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章，那么我一无所获。 以上来自于谷歌翻译 以下为原文 From UG380 section titled FPGA I/O Pin Settings During Configuration: ... However, all user I/O pins have optional pull-up resistors that can be enabled during the configuration process. During configuration, a single control line determines whether the pull-up resistors are enabled or disabled. The pin name is HSWAPEN Note that there is no provision for pull-down resistors during configuration, only pull-up resistors (disabled by HSWAPEN input). If you want User IOs to be LOW (instead of HIGH or Z) during configuration, you must provide external pulldown circuits. Driving HSWAPEN input pin LOW will enable the internal pull-up resistors on all User IO pins until configuration is completed. -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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谢谢鲍勃。
我删除了外部下拉组件，现在所有io引脚都处于低电平状态。 以上来自于谷歌翻译 以下为原文 Thanks Bob. I removed external pull down component now all io pins are low state. |
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shahulakthar写道：
谢谢鲍勃。 我删除了外部下拉组件，现在所有io引脚都处于低电平状态。 如果没有HSWAPEN的下拉，引脚将处于高阻态 - 不会被拉动 下。 如果您将它们测量为“低”，则可能是您的测量设备（范围或仪表） 拉下网。 你不应该依赖于非驱动的稳定低水平 销。 - Gabor - Gabor 以上来自于谷歌翻译 以下为原文 shahulakthar wrote:Without the pull-down of HSWAPEN, the pins will be in a high-impedance state - not pulled down. If you measure them "low" it's likely that your measuring device (scope or meter) is pulling down the nets. You should not depend on a solid low level from an un-driven pin. -- Gabor -- Gabor |
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你好鲍勃，能帮帮我吧。
我在配置期间启用I / O内部上拉电阻时遇到类似问题。 我有两个级别的功率为斯巴达6：银行0和1有1,8V供应，银行2和3 - 3,3V。 我将HSWAPEN引脚连接到1,8V（逻辑'1'），因为引脚位于0 bank内。 不过，我看到配置过程中我的I / O处于高电平状态。 但这对我的申请不利。 问题是什么？ 可能是我应该将HSWAPEN引脚拉至3.3V。 在配置期间，我使用SPI配置接口和SPI闪存设备。 问候， 瓦迪姆 以上来自于谷歌翻译 以下为原文 Hello Bob, could you please help me. I have a similar problem with enabled internal pull-ups for I/Os during configuration. I have two levels of power for Spartan6: Banks 0 and 1 have 1,8V supply whereas banks 2 and 3 - 3,3V. And I connect HSWAPEN pin to 1,8V (logic '1') because the pin is within 0 bank. Nevertheless, I see that my I/Os is in high level during configuration. But this is not good for my application. What is the problem? May be I should pull up HSWAPEN pin to 3,3V. During configuration I use SPI configuration interface with SPI flash device. Regards, Vadim |
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HSWAPEN引脚说明将其拉到ug380中的VCCO_0，所以我不愿意
建议将其连接到3.3V。 在配置期间，引脚可能有其他原因。 你是 确定是FPGA拉起来了吗？ 另请注意，当您使用Impact来使用间接编程SPI闪存时 SPI编程，FPGA已不再“正在配置”，因为它已被加载 使用特殊的“SPI编程内核”（比特流）通过JTAG访问闪存。 这个核心忽略了HSWAPEN上的设置并且始终是一个已知问题 将未使用的IOB设置为上拉。 - Gabor - Gabor 以上来自于谷歌翻译 以下为原文 The HSWAPEN pin description says to pull it to VCCO_0 in ug380, so I would not recommend tieing it to 3.3V. There may be other reasons why the pins are high during configuration. Are you sure it is the FPGA pulling them up? Also note that while you are using Impact to program the SPI flash using indirect SPI programming, the FPGA is no longer "being configured," as it has been loaded with a special "SPI programming core" (bitstream) to access the flash via JTAG. It is a known issue that this core ignores the settings on HSWAPEN and always sets the unused IOB's to pull-up. -- Gabor -- Gabor |
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你好Gabor。
是的我正在使用Impact来配置串行SPI，并且在配置过程中，所有IO（用于我的设计）被拉起。据我所知，在配置系统期间忽略HSWAPEN引脚。 这对我来说不好，我甚至在配置期间使用外部下拉电阻toset'0'。如何避免这种情况？ 是否可以使用Impact或可能是另一种工具？ 你写过“SPI编程核心”...... 问候， 瓦迪姆 以上来自于谷歌翻译 以下为原文 Hello Gabor. Yes I'm using Impact to configured serial SPI and during configuration process all IOs (that are used for my design) are pulled up. As far as I understand during the configuration system ignores HSWAPEN pin. This is not good for me, I'm even using external pull down resistors to set '0' during configuration. How to avoid this situation? Is it possible using Impact or may be another tool? You wrote about "SPI programming core"... Regards, Vadim |
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的Gabor，
顺便说一句，在配置期间使用的上拉电阻的价值是多少？ 瓦迪姆 以上来自于谷歌翻译 以下为原文 Gabor, by the way, what is the value of pull up resistors that are using during configutaion? Vadim |
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我建议你看一下这个帖子：
http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan-6-pull-ups-during-SPI-indirect-programming-using/td-p/201743 在这种情况下，Xilinx提供了一个没有上拉的变通核心。 关键是“核心”是真的 一个配置比特流，它被加载到你的FPGA中，以便将JTAG连接到 SPI闪存引脚。 据我所知，Xilinx不公布此设计的来源，或者您可以 使用适当的bitgen选项自行重建它以关闭未使用的IOB上的上拉。 此问题还有另外两种解决方法： 1）使用可用的电路板接口编写自己的SPI闪存上传器（我已经使用过 此异步串口为115,200波特）。 2）在电路板上添加一个连接器，直接访问SPI闪存并使用 廉价的第三方SPI程序员。 您可能需要添加跳线或FET开关 在编程时将闪光灯与电路板的其余部分隔离开来。 在这两种方法中，第一种方法具有可在其中使用的附加优点 没有任何Xilinx工具（软件或硬件）的字段。 - Gabor PS - 对于上拉“电阻”的值，您需要查看电气特性 您设备的数据表部分。 上拉表现得更像电流源 比电阻器，所以数据表发布最大电流而不是电流 电阻值。 另请注意，电流取决于组的Vcco电压。 您还可以从IBIS模型获得上拉的I-V曲线。 - Gabor 以上来自于谷歌翻译 以下为原文 I suggest you take a look at this thread: http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan-6-pull-ups-during-SPI-indirect-programming-using/td-p/201743 In this case, Xilinx provided a workaround core with no pullups. The point is that the "core" is really a configuration bitstream which gets loaded into your FPGA in order to connect the JTAG to the SPI flash pins. As far as I know, Xilinx does not publish the source for this design, or you could rebuild it yourself with the appropriate bitgen options to turn off pullups on unused IOB's. There are two other workarounds to this problem: 1) Write your own SPI flash uploader using an available interface to your board (I have used asynchronous serial ports at 115,200 Baud for this). 2) Add a connector to your board to access the SPI flash directly and program it using an inexpensive third-party SPI programmer. You may need to add jumpers or FET switches to isolate the flash from the rest of the board while programming. Of those two approaches, the first has the added advantage of being usable in the field without any Xilinx tools (software or hardware). -- Gabor PS - For the value of the pullup "resistors" you need to look at the electrical characterisics section of the data sheet for your device. The pullups behave more like current sources than like resistors, so the data sheet publishes the maximum current rather than the resistor value. Also note that the current depends on the Vcco voltage for the bank. You can also get the I-V curve for a pullup from the IBIS models. -- Gabor |
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全部，我在设计中也遇到了同样的问题。我的FPGA是SPartan 6XC6SLX16.problem我面临的是program_b。
由监控IC驱动。 根据UG380，该引脚的确切电压为0.9V.as旧设计，此引脚的值应为3.3V。到目前为止我做了什么：-1）我已经卸下了监控IC并提供了一个上拉电阻 在prog_b引脚上为3.3V，但仍未观察到时钟。 FPGA处于主串行模式，XCf04s闪存作为存储器芯片。 但是没有从闪存到FPGA的数据传输，因为闪存需要来自FPGA的cclk信号。 init引脚状态也很低 请告诉我你可能需要的其他细节可能出错了什么？ 以上来自于谷歌翻译 以下为原文 HI All, I m also facing the same issue within my design. my FPGA is SPartan 6 XC6SLX16. problem i'm facing is with program_b. which is driven by supervisory IC. the exact voltage at this pin is 0.9V. as per the UG380, and old design the value at this pin should be 3.3V. what have I done so far:- 1) i have unmounted the suervisory IC and provided a pull up of 3.3V at prog_b pin, but still no clock is observed. FPGA is in master serial mode with XCf04s flash as memory chip. but there is no data transfer from flash to FPGA, since flash need cclk signal from FPGA. init pin status is also low please let me know what other detail you might need what could have possibly gone wrong? |
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