请问Vivado会将设计流程从HDL架构转移到高级功能块生成器吗？

我应该先说一下，我已经离开 FPGA领域已经有几年了，并且对新一代的Xilinx硬件没有太多帮助。
我来自一所设计理念的学校，它重视低级别的可访问性，清晰度和简单性，我一直在关注Xilinx工具的发展和迷恋。
我早期的设计经验是使用Spartan-3和Virtex-IIProFPGAs。
对我来说，这些芯片的吸引力在于ISE的设计流程以及完全按照我的意愿设计设计的能力，可以自由地实现实现和语法错误（并由ISE指出）。
由于Xilinx已将设计师推向PlanAhead和Vivado，因此设计方向似乎朝着更高层次的方向发展，从设计师那里去除了设计控制的某些方面。
图形架构，C到VHDL HLS，以及（据我所知，我可能是错误的）完全改进的后端消除了简单地编写脚本并修改基于文本的配置文件的能力。
我注意到ISE已进入其生命的“持续”阶段。
这意味着，在未来的某个时刻，ISE的过时将成为一个真正的关注点，以及为其支持的硬件构建的能力。
ISE的最终消亡不仅是一个问题，而且能够获得廉价，简单，裸露的FPGA，只需很少的花哨，如Spartan-6，可以用简单的文本编辑器编写，似乎也在养育
它的头。
所以我想我的问题就是这些。
ISE需要支持多长时间？
Spartan-6可以使用多长时间？
有没有计划维护一系列简单的，精简的FPGA？
Vivado中是否有（或现在有）选项可以恢复到像Project Navigator这样的低级HDL / UCF设计流程用于裸逻辑设计？
或者Vivado会继续将设计流程从HDL架构转移到高级功能块生成器吗？
谢谢你的时间。



以下为原文

I should preface this by saying that I've been out of the FPGA field for a couple of years now, and haven't worked much with newer genera tions of Xilinx hardware.

I come from a school of design philosophy that values low-level accessibility, clarity, and simplicity, and I've been watching the progression of Xilinx tools with fascination and a small measure of concern. My early design experiences were with Spartan-3 and Virtex-II Pro FPGAs. For me, the appeal of those chips was the design flow of ISE and the ability to architect a design exactly as I wanted, free to make implementation and syntax errors (and have them pointed out by ISE). As Xilinx has pushed designers toward PlanAhead and then Vivado, it seems like the direction of design is going towards a higher-level picture that removes some aspects of design control from the designer. Graphical architecture, C to VHDL HLS, and a completely revamped backend that (to my knowledge, I could be wrong) eliminates the ability to simply script builds and modify text-based configuration files.

I notice that ISE has entered the "sustaining" phase of its life. This implies that at some point down the road, obsolescence of ISE will become a genuine concern, along with the ability to build for its supported hardware. Not only is the eventual demise of ISE a concern, but the ability to obtain cheap, simple, bare FPGAs with few bells and whistles like the Spartan-6 that can be written for with something as simple as a text editor also seems to be rearing its head.

So I guess my questions are these. How long will ISE be supported? How long will the Spartan-6 be available? Are there any plans to maintain a line of simple, stripped-down FPGAs? Will there ever be (or is there now) an option in Vivado to revert to a low-level HDL/UCF design flow like Project Navigator for bare logic designs? Or will Vivado just continue to move design flow from an HDL architecture to a high level function block generator?

Thanks for your time.