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EDA简介（Eng）

2011-10-11 16:24:24 3499

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[/url] [url=http://en.wikipedia.org/wiki/File:Kicad_Pcbnew_screenshot.jpg]
PCB layout program

Electronic design automation (EDA or ECAD) is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips.
This article describes EDA specifically with respect to integrated circuits.

Contents

1 History

1.1 Early days

1.2 Birth of commercial EDA

1.3 Current status

2 Software focuses

2.1 Design

2.2 Simulation

2.3 Analysis and verification

2.4 Manufacturing preparation

3 Companies

3.1 Top companies

3.2 Acquisitions

4 See also

5 References

[edit] History[edit] Early daysBefore EDA, integrated circuits were designed by hand, and manually laid out. Some advanced shops used geometric software to generate the tapes for the Gerber photoplotter, but even those copied digital recordings of mechanically-drawn components. The process was fundamentally graphic, with the translation from electronics to graphics done manually. The best known company from this era was Calma, whose GDSII format survives.
By the mid-70s, developers started to automate the design, and not just the drafting. The first placement and routing (Place and route) tools were developed. The proceedings of the Design Automation Conference cover much of this era.
The next era began about the time of the publication of "Introduction to VLSI Systems" by Carver Mead and Lynn Conway in 1980. This ground breaking text advocated chip design with programming languages that compiled to silicon. The immediate result was a considerable increase in the complexity of the chips that could be designed, with improved access to design verification tools that used logic simulation. Often the chips were easier to lay out and more likely to function correctly, since their designs could be simulated more thoroughly prior to construction. Although the languages and tools have evolved, this general approach of specifying the desired behavior in a textual programming language and letting the tools derive the detailed physical design remains the basis of digital IC design today.
The earliest EDA tools were produced academically. One of the most famous was the "Berkeley VLSI Tools Tarball", a set of UNIX utilities used to design early VLSI systems. Still widely used is the Espresso heuristic logic minimizer and Magic.
Another crucial development was the formation of MOSIS, a consortium of universities and fabricators that developed an inexpensive way to train student chip designers by producing real integrated circuits. The basic concept was to use reliable, low-cost, relatively low-technology IC processes, and pack a large number of projects per wafer, with just a few copies of each projects' chips. Cooperating fabricators either donated the processed wafers, or sold them at cost, seeing the program as helpful to their own long-term growth.
[edit] Birth of commercial EDA1981 marks the beginning of EDA as an industry. For many years, the larger electronic companies, such as Hewlett Packard, Tektronix, and Intel, had pursued EDA internally. In 1981, managers and developers spun out of these companies to concentrate on EDA as a business. Daisy Systems, Mentor Graphics, and Valid Logic Systems were all founded around this time, and collectively referred to as DMV. Within a few years there were many companies specializing in EDA, each with a slightly different emphasis. The first trade show for EDA was held at the Design Automation Conference in 1984.
In 1986, Verilog, a popular high-level design language, was first introduced as a hardware description language by Gateway Design Automation. In 1987, the U.S. Department of Defense funded creation of VHDL as a specification language. Simulators quickly followed these introductions, permitting direct simulation of chip designs: executable specifications. In a few more years, back-ends were developed to perform logic synthesis.
[/url] [url=http://en.wikipedia.org/wiki/File:Kicad_Pcbnew3D_screenshot.jpg]
3D PCB layout

[edit] Current statusCurrent digital flows are extremely modular (see Integrated circuit design, Design closure, and Design flow (EDA)). The front ends produce standardized design descriptions that compile into invocations of "cells,", without regard to the cell technology. Cells implement logic or other electronic functions using a particular integrated circuit technology. Fabricators generally provide libraries of components for their production processes, with simulation models that fit standard simulation tools. Analog EDA tools are far less modular, since many more functions are required, they interact more strongly, and the components are (in general) less ideal.
EDA for electronics has rapidly increased in importance with the continuous scaling of semiconductor technology.[citation needed] Some users are foundry operators, who operate the semiconductor fabrication facilities, or "fabs", and design-service companies who use EDA software to evaluate an incoming design for manufacturing readiness. EDA tools are also used for programming design functionality into FPGAs.
[edit] Software focuses[edit] DesignMain article: Design flow (EDA)

High-level synthesis(syn. behavioural synthesis, algorithmic synthesis) For digital chips
Logic synthesis translation of abstract, logical language such as Verilog or VHDL into a discrete netlist of logic-gates
Schematic Capture For standard cell digital, analog, rf like Capture CIS in Orcad by CADENCE and ISIS in proteus
Layout like Layout in Orcad by Cadence, ARES in Proteus

[edit] SimulationMain article: Electronic circuit simulation

Transistor simulation – low-level transistor-simulation of a schematic/layout's behavior, accurate at device-level.
Logic simulation – digital-simulation of an RTL or gate-netlist's digital (boolean 0/1) behavior, accurate at boolean-level.
Behavioral Simulation – high-level simulation of a design's architectural operation, accurate at cycle-level or interface-level.
Hardware emulation – Use of special purpose hardware to emulate the logic of a proposed design. Can sometimes be plugged into a system in place of a yet-to-be-built chip; this is called in-circuit emulation.
Technology CAD simulate and analyze the underlying process technology. Electrical properties of devices are derived directly from device physics.
Electromagnetic field solvers, or just field solvers, solve Maxwell's equations directly for cases of interest in IC and PCB design. They are known for being slower but more accurate than the layout extraction above.

[/url] [url=http://en.wikipedia.org/wiki/File:Kicad_Eeschema_screenshot.jpg]
Schematic capture program

[edit] Analysis and verification

Functional verification
Clock Domain Crossing Verification (CDC check): Similar to linting, but these checks/tools specialize in detecting and reporting potential issues like data loss, meta-stability due to use of multiple clock domains in the design.
Formal verification, also model checking: Attempts to prove, by mathematical methods, that the system has certain desired properties, and that certain undesired effects (such as deadlock) cannot occur.
Equivalence checking: algorithmic comparison between a chip's RTL-description and synthesized gate-netlist, to ensure functional equivalence at the logical level.
Static timing analysis: Analysis of the timing of a circuit in an input-independent manner, hence finding a worst case over all possible inputs.
Physical verification, PV: checking if a design is physically manufacturable, and that the resulting chips will not have any function-preventing physical defects, and will meet original specifications.

[edit] Manufacturing preparation

Mask data preparation, MDP: generation of actual lithography photomask used to physically manufacture the chip.
- Resolution enhancement techniques, RET – methods of increasing of quality of final photomask.
- Optical proximity correction, OPC – up-front compensation for diffraction and interference effects occurring later when chip is manufactured using this mask.
- Mask generation – generation of flat mask image from hierarchical design.
- Automatic test pattern generation, ATPG – generates pattern-data to systematically exercise as many logic-gates, and other components, as possible.
- Built-in self-test, or BIST – installs self-contained test-controllers to automatically test a logic (or memory) structure in the design

[/url] [url=http://en.wikipedia.org/wiki/File:Gschem_and_gerbv.jpg]
PCB layout and schematic for connector design

[edit] CompaniesFor more details on this topic, see List of EDA companies.
[edit] Top companies

$3.85 billion - Synopsys
$2.80 billion - Cadence
$1.49 billion - Mentor Graphics
$506 million - Magma Design Automation
¥13.22 billion - Zuken Inc.

Note: Market caps current as of June, 2011.[1] EEsof should likely be on this list,[2] but does not have a market cap as it is the EDA division of Agilent.
[edit] AcquisitionsMany of the EDA companies acquire small companies with software or other technology that can be adapted to their core business.[3] Most of the market leaders are rather incestuous amalgamations of many smaller companies. This trend is helped by the tendency of software companies to design tools as accessories that fit naturally into a larger vendor's suite of programs on digital circuitry, many new tools incorporate analog design, and mixed systems. This is happening because there is now a trend to place entire electronic systems on a single chip.
[edit] See also

[/url]

[url=http://en.wikipedia.org/wiki/Portal:Electronics]Electronics portal

[edit] References

http://www.google.com/finance?q=TYO:6947,NASDAQ:LAVA,NASDAQ:MENT,NASDAQ:SNPS,NASDAQ:CDNS

"Agilent EEsof EDA – Part I"

http://www10.edacafe.com/nbc/articles/view_weekly.php?articleid=782353

^ Kirti Sikri Desai (2006). "EDA Innovation through Merger and Acquisitions". EDA Cafe. http://www10.edacafe.com/nbc/articles/view_article.php?articleid=301031&interstitial_displayed=Yes. Retrieved March 23, 2010.

Notes

http://www.staticfreesoft.com/documentsTextbook.html Computer Aids for VLSI Design by Steven M. Rubin
Electronic Design Automation For Integrated Circuits Handbook, by Lavagno, Martin, and Scheffer, ISBN 0-8493-3096-3, 2006
Combinatorial Algorithms for Integrated Circuit Layout, by Thomas Lengauer, ISBN 3-519-02110-2, Teubner Verlag, 1997.
The Electronic Design Automation Handbook, by Dirk Jansen et al., Kluwer Academic Publishers, ISBN 1-4020-7502-2, 2003, available also in German ISBN 3-446-21288-4 (2005)

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2011-10-11 16:24:24　　评论 淘帖0 举报

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2011-10-11 17:03:21 评论举报 1^# wangka

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2011-10-12 16:12:05 评论举报 2^# 崔立学

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2013-5-7 22:31:42 评论举报 3^# 苏颜语

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