[问答]

ARMv8 Vector table问题该如何更好地去理解呢

2053 ARM处理器 SoC芯片

问答对人有帮助，内容完整，我也想知道答案0 目前正在学习ARMv8 Arch Ref Manual. D1.10.2 Exception vectors有点疑惑： Table D1-6 定义了一个Vector Table应该具有的items 我们假定一个ARMv8 SOC实现了4个EL：EL0 / EL1 / EL2 / EL3 根据ARMv8 ARM手册：每一个EL，都有自己对应的Vector Table. 那么： EL0 / EL1 / EL2 / EL3 :它们各自的Vector Table，应该是什么样的？比如： (1) EL0的Vector Table：应该有2个Block : Current Exception level with SP_EL0 Current Exception level with SP_ELx, x>0 (2) EL1的Vector Table：应该有4个Block : Current Exception level with SP_EL0 Current Exception level with SP_ELx, x>0 EL0 that is using AARCH64 EL0 that is using AARCH32 我的理解对吗？ 0
2022-8-17 15:54:07　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × hgimtk 该类别下有 16 个回答。邀请回答 dianzijie5 该类别下有 16 个回答。邀请回答嵌入式-H 该类别下有 16 个回答。邀请回答 hucc 该类别下有 14 个回答。邀请回答舍我其谁84 该类别下有 13 个回答。邀请回答 HCPcry 该类别下有 12 个回答。邀请回答冰箱洗衣机该类别下有 12 个回答。邀请回答小刘该类别下有 11 个回答。邀请回答 sjjs001 该类别下有 11 个回答。邀请回答 iettke 该类别下有 11 个回答。邀请回答学生物的程序猿该类别下有 11 个回答。邀请回答 YOYOOO 该类别下有 10 个回答。邀请回答 bigbangboom 该类别下有 10 个回答。邀请回答 siyugege 该类别下有 9 个回答。邀请回答 drakannie 该类别下有 9 个回答。邀请回答 wuli北该类别下有 9 个回答。邀请回答 zengweishuai 该类别下有 9 个回答。邀请回答广州洋钒该类别下有 9 个回答。邀请回答 felixbury 该类别下有 8 个回答。邀请回答 h1654155957.9921 该类别下有 8 个回答。邀请回答举报最强海贼王相关推荐 • 请问如何理解ARMv8内存属性device5402 • NEON在armv8(arch64)下如何去使用呢2710 • 怎样在PC机器上编译RK3566ARMv8平台的代码呢2048 • 在armv8架构中Arch32切换到Arch64是如何运作的1992 •ARMv8架构的两种执行状态分别是什么4945 • 为什么访问ARMV8系统寄存器icc_sre_el2会发生错误呢1965 • Arm各个exception level都可以访问sp_el0, 这么做的原因是什么？1408 • ARM究竟有没有美国的技术？2217 • 请问怎么理解ARMv7的Secure和Non-secure状态3758 • 请问linux entry/armv.S 中的vector_\name是什么意思？2210 1个回答

答案对人有帮助，有参考价值0 EL0 does not have a vector table. Only EL1, EL2 and EL3 have vector tables. The location is set by VBAR_EL1, VBAR_EL2 and VBAR_EL3 respectively. Each vector table has the same format, i.e. 16 entries (1 entry = 128 bytes) grouped into 4 blocks. Starting from the lowest offset, each block is used for exceptions taken from: Current Exception level with SP_EL0 Current Exception level with SP_ELx, x>0. Lower Exception level, where the implemented level immediately lower than the target level is using AArch64 Lower Exception level, where the implemented level immediately lower than the target level is using AArch32 Consider an IRQ from an AArch32 application (EL0) running on an AArch64 OS (EL1), being handled by an AArch64 hypervisor (EL2). In this case, the exception will be "from AArch32", but the hypervisor must save all the AArch64 states, as they may contain active values for the OS. Therefore, the exception entry for this case would be: VBAR_EL2 + 0x480

2022-8-17 15:54:25 评论举报李敏