modelsim仿真的问题

我看夏宇闻老师的《Verilog 数字系统设计教程》第十一章例组合逻辑二一个三态数据通路控制器

代码：

`defineON1'b1`defineOFF1'b0modulezhlj2(LinkBusSwitch,outbuf,inbuf,bus,clk); input LinkBusSwitch; input[7:0] outbuf; output [7:0] inbuf; input clk; inout [7:0] bus; wire LinkBusSwitch; wire [7:0] outbuf; reg [7:0] inbuf; wire [7:0] bus; assign bus=(LinkBusSwitch == `ON) ? outbuf :8'hzz;always @(posedge clk) beginif(!LinkBusSwitch) inbuf<=bus;endendmodule

仿真代码：

`timescale1ns/1ps module zhlj2_vlg_tst();// constants// general purpose registers//reg eachvec;// test vector input registers//reg [7:0] treg_bus;reg clk; reg [7:0] outbuf;// wiresreg LinkBusSwitch; wire [7:0] bus; wire [7:0] inbuf;// assign statements (if any)//assign bus = treg_bus;zhlj2 i1 (// port map - connection between master ports and signals/registers.LinkBusSwitch(LinkBusSwitch), .bus(bus), .clk(clk), .inbuf(inbuf), .outbuf(outbuf) ); initial begin// code that executes only once// insert code here --> begin//beginLinkBusSwitch=0; clk=0;//endforever#5 clk=~clk;end// --> endinitial begin#20 outbuf=15;#20 outbuf=38;#20 LinkBusSwitch=1;#20 outbuf=122;#20 outbuf=238;#20 outbuf=72;#20 LinkBusSwitch=0;#20 outbuf=55;#20 outbuf=0;$finish; end endmodule

有一处波形不对，就是outbuf=238时，显示-18.

波形图如下：

请问高手，怎么回事？谢谢！