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小弟刚来贵论坛，也没有什么能感谢大家的，就只能在此先说一声谢谢了。
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六十进制
module count60(clock,rst,countnum); input clock,rst; output [5:0] countnum; reg [5:0] countnum; always @(posedge clock) begin if (rst) countnum <= 6'b000000; else begin if (countnum ==59) countnum <= 6'b000000; else countnum <= countnum +1'b1; end end endmodule |
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主控制程序
module controller(clk,cnum,startew,startsn, rede,redw,reds,redn,greene,greenw,greens,greenn); input clk; input [5:0] cnum; output startew,startsn; output rede,redw,reds,redn,greene,greenw,greens,greenn; reg startew,startsn; reg rede,redw,reds,redn,greene,greenw,greens,greenn; always @(posedge clk) begin if (cnum == 0) begin startsn <= 1'b1; startew <= 1'b0; end else if ((cnum >=1) &&(cnum <= 24)) begin startsn <=1'b0; startew <= 1'b0; reds <= 1'b1; redn <= 1'b1; greene <= 1'b1; greenw <= 1'b1; rede <= 1'b0; redw <= 1'b0; greens <= 1'b0; greenn <= 1'b0; end else if ((cnum >24) &&(cnum < 30)) begin startsn <= 1'b0; startew <= 1'b0; reds <= 1'b1; redn <= 1'b1; greene <= 1'b0; greenw <= 1'b0; rede <= 1'b1; redw <= 1'b1; greens <= 1'b0; greenn <= 1'b0; end begin startsn <= 1'b0; startew <= 1'b1; end else if ((cnum >30) &&(cnum <= 59)) begin startsn <= 1'b0; startew <= 1'b0; reds <= 1'b0; redn <= 1'b0; greene <= 1'b0; greenw <= 1'b0; rede <= 1'b1; redw <= 1'b1; greens <= 1'b1; greenn <= 1'b1; end else begin startsn <= 1'b0; startew <= 1'b0; reds <= 1'b0; redn <= 1'b0; greene <= 1'b0; greenw <= 1'b0; rede <= 1'b0; redw <= 1'b0; greens <= 1'b0; greenn <= 1'b0; end end endmodule |
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分位倒计时显示控制
module anticount( clock,startp,data1,data2,enable); input clock,startp; output enable; output [3:0] data2,data1; reg [3:0] data2,data1; reg [4:0] count; reg enable; always @(posedge startp or negedge clock) begin if (startp) enable <= 1'b1; else if (count == 0) enable <= 1'b0; end always @(posedge clock) begin if (enable) begin if ( count == 0) count = 5'b11110; // 设置倒计时值30秒 else count <= count -1'b1; end else count <= 5'b00000; end always @(negedge clock) begin if (enable) begin data2 <= count/10; data1 <= count%10; end else begin data2 <= 4'b0000; data1 <= 4'b0000; end end endmodule |
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100分频模块
module fredevider100(clockin,clockout); input clockin; output clockout; reg[6:0] count; reg clockout; parameter N=49; always@(posedge clockin) begin if(count==N) begin count<=7'b0000000; clockout<=~clockout; end else count<=count+7'b0000001; end endmodule |
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有点复杂啊
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module fredevider100(clockin,clockout);
input clockin; output clockout; reg[6:0] count; reg clockout; parameter N=49; |
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woyeganglai,软件都不知道发哦该下载那个
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2014-2-26 14:40:54
评论
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只有小组成员才能发言，加入小组>>
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写了一个用DMA读取ADC数据的程序，记录下整个过程和一点心得
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