刚接触FPGA的菜鸟，哪位能帮忙看下这段秒表的代码，为什么数码管一直显示全为0.

module stopwatch (clk,out,reset,cin,ocom);
output [3:0] ocom;
output [7:0] out;
input cin,clk,reset;
reg [7:0] out_ms,out_s;
reg [7:0] out;
reg [3:0] ocom;
reg [3:0] in_out;
reg clk_m,clk_n,clk_p;
reg [1:0] select;
reg [15:0] count_clk,count_cp,count_tp;

always @ (posedge clk)
begin
if(count_cp==48000) //48MHZ做 48000次分频，取反后得到2ms的时间
begin
count_tp=0;
clk_n=~clk_n;
end
else
count_cp=count_cp+1;
end

always @ (posedge clk)
begin
if(count_clk==24000000) //48MHZ做24000000次分频，取反后得到1s的时间
begin
count_clk=0;
clk_m=~clk_m;
end
else
count_clk=count_clk+1;
end

always @ (posedge clk)
begin
if(count_tp==240000) //48MHZ做240000次分频，取反后得到0.01s的时间
begin
count_tp=0;
clk_p=~clk_p;
end
else
count_tp=count_tp+1;
end

always @ (posedge clk_n) //2ms的数码管的扫描

select=select+1;

always @ (select) //数码管的扫描
begin
case(select)
2'b00:begin ocom[3:0]=4'b1110;in_out=out_ms[3:0];end
2'b01:begin ocom[3:0]=4'b1101;in_out=out_ms[7:4];end
2'b10:begin ocom[3:0]=4'b1011;in_out=out_s[3:0];end
2'b11:begin ocom[3:0]=4'b0111;in_out=out_s[7:4];end
endcase
end

always @ (posedge clk_p or negedge reset)
begin
if(!reset) //若reset为低电平，四位数码管清零
begin
out_ms<=0;
out_s<=0;
end
else if(cin)
begin
if(out_ms[3:0]==9)
begin
out_ms[3:0]<=0;
if(out_ms[7:4]==9)
begin
out_ms[7:4]<=0;
if(out_s[3:0]==9)
begin
out_s[3:0]<=0;
if(out_s[7:4]==5)
out_s[7:4]<=0;
else
out_s[7:4]<=out_s[7:4]+1;
end
else
out_s[3:0]<=out_s[3:0]+1;
end
else
out_ms[7:4]<=out_ms[7:4]+1;
end
else
out_ms[3:0]<=out_ms[3:0]+1;
end
end

always @ (in_out)
begin
case(in_out) //将要显示的数字译成段码
4'b0000://0
out[7:0]=8'b0000_0011;
4'b0001://1
out[7:0]=8'b1001_1111;
4'b0010://2
out[7:0]=8'b0010_0101;
4'b0011://3
out[7:0]=8'b0000_1101;
4'b0100://4
out[7:0]=8'b1001_1001;
4'b0101://5
out[7:0]=8'b0100_1001;
4'b0110://6
out[7:0]=8'b0100_0001;
4'b0111://7
out[7:0]=8'b0001_1111;
4'b1000://8
out[7:0]=8'b0000_0001;
4'b1001://9
out[7:0]=8'b0000_1001;
default: //这里仅编译了0-9这几个数字
out[7:0]=8'b1111_1111; //全灭
endcase
end
endmodule




为什么四位数码管一直显示的为零