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NXP公司的LPCXpresso54628是基于ARM Cortex-M4核的低功耗MCU,具有丰富外设,非常低功耗和增强的调试特性.ARM Cortex-M4 CPU采用3级流水线,具有单独本地指令和数据总线以及用于外设的第三总线的哈佛架构,支持单周期数字信号处理和SIMD指令,内核还集成了硬件浮点处理器.LPC546xx系列产品包括512KB闪存,200KB SRAM,多达16kB EEPROM,四个SPI闪存接口(SPIFI),高速和全速USB主和设备控制器,以太网AVB,LCD控制器,智能卡接口,SD/MMC,CAN FD和外接存储器控制器(EMC),带PDM麦克风接口和I2S的DMIC子系统,五个通用计时器, SCTimer/PWM,RTC/告警计时器,多速率计时器(MRT),视窗看门狗计时器(WWDT),十个灵活串行通报批评信外设(USART, SPI, I2S, I2C接口),安全散列算法(SHA),12位5.0MSPS ADC和温度传感器.主要用于嵌入式应用.本文介绍了LPCXpresso546xx系列主要特性,框图,以及LPCXpresso546xx评估板主要特性和电路图.
The LPC546xx is a family of ARM Cortex-M4 based microcontrollers for embeddedpplications featuring a rich peripheral set with very low power consumption andenhanced debug features.The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated into the core.
The LPC546xx family includes up to 512 KB of flash, 200 KB of on-chip SRAM, up to 16 kB of EEPROM memory, a quad SPI Flash Interface (SPIFI) for expanding program memory, one high-speed and one full-speed USB host and device controller, Ethernet AVB, LCD controller, Smart Card Interfaces, SD/MMC, CAN FD, an External Memory Controller (EMC), a DMIC subsystem with PDM microphone interface and I2S, five general-purpose timers, SCTimer/PWM, RTC/alarm timer, Multi-Rate Timer (MRT), a Windowed Watchdog Timer (WWDT), ten flexible serial communication peripherals(USART, SPI, I2S, I2C interface), Secure Hash Algorithm (SHA), 12-bit 5.0 Msamples/sec ADC, and a temperature sensor.
LPCXpresso54628主要特性:
ARM Cortex-M4 core (version r0p1):
ARM Cortex-M4 processor, running at a frequency of up to 220 MHz.
The LPC5460x/61x devices operate at CPU frequencies of up to 180 MHz. The
LPC54628 device operates at CPU frequencies of up to 220 MHz.
Floating Point Unit (FPU) and Memory Protection Unit (MPU).
ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
Non-maskable Interrupt (NMI) input with a selection of sources.
Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators,and four watch points. Includes Serial Wire Output and ETM Trace for enhanceddebug capabilities, and a debug timestamp counter.
System tick timer.
On-chip memory:
Up to 512 KB on-chip flash program memory with flash accelerator and 256 bytepage erase and write.
Up to 200 KB total SRAM consisting of 160 KB contiguous main SRAM and anadditional 32 KB SRAM on the I&D buses. 8 KB of SRAM bank intended for USBtraffic.
16 KB of EEPROM.
ROM API support:
Flash In-Application Programming (IAP) and In-System Programming (ISP).
ROM-based USB drivers (HID, CDC, MSC, and DFU). Flash updates via USB.
Booting from valid user code in flash, USART, SPI, and I2C.
Legacy, Single, and Dual image boot.
OTP API for programming OTP memory.
Random Number Generator (RNG) API.
Serial interfaces:
Flexcomm Interface contains up to ten serial peripherals. Each Flexcomm Interface can be selected by software to be a USART, SPI, or I2C interface. Two Flexcomm Interfaces also include an I2S interface. Each Flexcomm Interface includes a FIFO that supports USART, SPI, and I2S if supported by that Flexcomm Interface. Avariety of clocking options are available to each Flexcomm Interface and include ashared fractional baud-rate generator.
I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to
1Mbit/s and with multiple address recognition and monitor mode. Two sets of trueI2C pads also support High Speed Mode (3.4 Mbit/s) as a slave.
Two ISO 7816 Smart Card Interfaces with DMA support.
USB 2.0 high-speed host/device controller with on-chip high-speed PHY.
USB 2.0 full-speed host/device controller with on-chip PHY and dedicated DMAcontroller supporting crystal-less operation in device mode.
SPIFI with XIP feature uses up to four data lines to access off-chip SPI/DSPI/QSPI
flash memory at a much higher rate than standard SPI or SSP interfaces.
Ethernet MAC with MII/RMII interface with Audio Video Bridging (AVB) support and dedicated DMA controller.
Two CAN FD modules with dedicated DMA controller.
Digital peripherals:
DMA controller with 30 channels and up to 24 programmable triggers, able toaccess all memories and DMA-capable peripherals.
LCD Controller supporting both Super-Twisted Nematic (STN) and Thin-FilmTransistor (TFT) displays. It has a dedicated DMA controller, selectable displayresolution (up to 1024 x 768 pixels), and supports up to 24-bit true-color mode.
External Memory Controller (EMC) provides support for asynchronous staticmemory devices such as RAM, ROM and flash, in addition to dynamic memoriessuch as single data rate SDRAM with an SDRAM clock of up to 100 MHz. EMC buswidth (bit) on LQFP100 and TFBGA100 packages supports up to 8/16 data linewide static memory, in addition to dynamic memories, such as, SDRAM (2 banksonly) with an SDRAM clock of up to 100 MHz.
Secured digital input/output (SD/MMC and SDIO) card interface with DMA support.
CRC engine block can calculate a CRC on supplied data using one of threestandard polynomials with DMA support.
Up to 171 General-Purpose Input/Output (GPIO) pins.
GPIO registers are located on the AHB for fast access. The DMA supports GPIOports.
Up to eight GPIOs can be selected as Pin Interrupts (PINT), triggered by rising,falling or both input edges.
Two GPIO Grouped Interrupts (GINT) enable an interrupt based on a logical(AND/OR) combination of input states.
CRC engine.
Analog peripherals:
12-bit ADC with 12 input channels and with multiple internal and external trigger
inputs and sample rates of up to 5.0 MSamples/sec. The ADC supports two
independent conversion sequences.
Integrated temperature sensor connected to the ADC.
DMIC subsystem including a dual-channel PDM microphone interface, flexible
decimators, 16 entry FIFOs, optional DC locking, hardware voice activity detection,and the option to stream the processed output data to I2S.
Timers:
Five 32-bit general purpose timers/counters, four of which support up to fourcapture inputs and four compare outputs, PWM mode, and external count input.
Specific timer events can be selected to generate DMA requests. The fifth timerdoes not have external pin connections and may be used for internal timingoperations.
SCTimer/PWM with 8 input and 10 output functions (including capture and match).
Inputs and outputs can be routed to/from external pins and internally to or fromselected peripherals. Internally, the SCTimer/PWM supports 10 match/captures, 10events, and 10 states.
32-bit Real-time clock (RTC) with 1 s resolution running in the always-on powerdomain. A timer in the RTC can be used for wake-up from all low power modesincluding deep power-down, with 1 ms resolution.
Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation atup to four programmable, fixed rates.
Windowed Watchdog Timer (WWDT).
Repetitive Interrupt Timer (RIT) for debug time stamping and for general purposeuse.
Security features:
enhanced Code Read Protection (eCRP) to protect user code.
OTP memory for ECRP settings, and user application specific data.
Secure Hash Algorithm (SHA1/SHA2) module with dedicated DMA controller.
Clock generation:
12 MHz internal Free Running Oscillator (FRO). This oscillator provides aselectable 48 MHz or 96 MHz output, and a 12 MHz output (divided down from theselected higher frequency) that can be used as a system clock. The FRO istrimmed to +/-1 % accuracy over the entire voltage and temperature range.
External clock input for clock frequencies of up to 25 MHz.
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
Watchdog Oscillator (WDTOSC) with a frequency range of 6 kHz to 1.5 MHz.
32.768 kHz low-power RTC oscillator.
System pll allows CPU operation up to the maximum CPU rate and can run from
the main oscillator, the internal FRO, the watchdog oscillator or the 32.768 KHzRTC oscillator.
Two additional PLLs for USB clock and audio subsystem.
Independent clocks for the SPIFI interface, ADC, USBs, and the audio subsystem.
Clock output function with divider.
Frequency measurement unit for measuring the frequency of any on-chip oroff-chip clock signal.
Power control:
Programmable PMU (Power Management Unit) to minimize power consumptionand to match requirements at different performance levels.
Reduced power modes: sleep, deep-sleep, and deep power-down.
Wake-up from deep-sleep modes due to activity on the USART, SPI, and I2Cperipherals when operating as slaves.
Ultra-low power Micro-tick Timer, running from the Watchdog oscillator that can beused to wake up the device from low power modes.
Power-On Reset (POR).
Brown-Out Detect (BOD) with separate thresholds for interrupt and forced reset.
Single power supply 1.71 V to 3.6 V.
Power-On Reset (POR).
Brown-Out Detect (BOD) with separate thresholds for interrupt and forced reset.
JTAG boundary scan supported.
128 bit unique device serial number for identification.
Operating temperature range -40 ℃ to +105 ℃.
Available in TFBGA180, TFBGA100, LQFP208, and LQFP100 packages
![[原创] NXP LPCXpresso54628低功耗ARM MCU开发方案](/uploads/allimg/180206/16243030K_0.png)
图1. LPCXpresso54628框图
![[原创] NXP LPCXpresso54628低功耗ARM MCU开发方案](/uploads/allimg/180206/162501V45_0.png)
图2. LPCXpresso546xx电源,时钟和调试连接图
LPCXpresso54608/54618/54628评估板
The LPCXpresso™ family of boards provides a powerful and flexible development system for NXP’s LPC Cortex®-M family of MCUs. They can be used with a wide range of development tools, including NXP’s MCUXpresso IDE. The LPCXpresso54608 (OM13092), LPCXpresso54618 (board provided as part of the OM13094 CAN-FD Kit) and LPCXpresso54628 (OM13098) share the same design and have been developed by NXP to enable evaluation of and prototyping with the LPC546xx family of MCUs. There is no functional difference between these boards except the (1) functionality of the LPC546xx device installed, and (2) that the LPC54618 board included in the OM13094 does not include the LCD panel. All boards use a BGA180 package.
Note that the LPCXpresso54628 board features an LPC54628 device which has a superset of functionality compared to the LPC54608 and LPC54618. This means code written for the LPC54608 and LPC54618 can run unchanged on the LPC54628. The LPC54628 is capable of running at up to 220MHz, but requires a different power library (from the MCUXpresso SDK) than the other devices in order to run at this clock speed. Initially this library will be available as a separate download until it is fully integrated into the SDK in Q4 2017.
The schematics show that the board was designed for either 1.8 V or 3.3 V build configurations, but all production boards are built in the 3.3 V configuration.
LPCXpresso546xx评估板主要特性:
• On-board, high-speed USB based, Link2 Debug Probe with CMSIS-DAP and SEGGER J-Link protocol options: Link2 probe can be used with on-board LPC546xx or external target.
UART and SPI port bridging from LPC546xx target to USB via the on-board Debug Probe.
Support for external Debug Probe.
• 3 x user LEDs
• Target Reset, ISP (3) and user buttons
• Expansion options based on popular standards: Arduino UNO compatible expansion site with additional LPCXpresso V3 standard connections
PMod™ compatible expansion port
Host connection / general purpose expansion port
• On-board 3.3V regulator with external power supply options.
• Built-in power consumption measurement for target LPC546xx MCU.
• 128Mb Micron MT25QL128 Quad-SPI flash.
• 128Mb Micron MT48LC8M16A2B4 SDRAM.
• Knowles SPH0641LM4H digital microphone.
• Full size SD/MMC card slot.
• NXP MMA8652FCR1 accelerometer.
• Stereo audio codec with line in/out.
• High and full speed USB ports with micro A/B connector for host or device functionality.
• 10/100Mbps Ethernet (RJ45 connector).
• 272x480 color LCD with capacitive touch screen.
图3.LPCXpresso546xx评估板底视图
![[原创] NXP LPCXpresso54628低功耗ARM MCU开发方案](/uploads/allimg/180206/162531Q00_0.png)
图4.LPCXpresso546xx评估板主要特性分布图
![[原创] NXP LPCXpresso54628低功耗ARM MCU开发方案](/uploads/allimg/180206/16255L932_0.png)
图5.LPCXpresso546xx评估板电路图(1)
![[原创] NXP LPCXpresso54628低功耗ARM MCU开发方案](/uploads/allimg/180206/1626015R8_0.png)
图6.LPCXpresso546xx评估板电路图(2)
![[原创] NXP LPCXpresso54628低功耗ARM MCU开发方案](/uploads/allimg/180206/16262T647_0.png)
图7.LPCXpresso546xx评估板电路图(3)
![[原创] NXP LPCXpresso54628低功耗ARM MCU开发方案](/uploads/allimg/180206/162AUI6_0.png)
图8.LPCXpresso546xx评估板电路图(4)
![[原创] NXP LPCXpresso54628低功耗ARM MCU开发方案](/uploads/allimg/180206/162F26451_0.png)
图9.LPCXpresso546xx评估板电路图(5)
![[原创] NXP LPCXpresso54628低功耗ARM MCU开发方案](/uploads/allimg/180206/162HU923_0.png)
图10.LPCXpresso546xx评估板电路图(6)
![[原创] NXP LPCXpresso54628低功耗ARM MCU开发方案](/uploads/allimg/180206/162KQ2Q_0.png)
图11.LPCXpresso546xx评估板电路图(7)
![[原创] NXP LPCXpresso54628低功耗ARM MCU开发方案](/uploads/allimg/180206/162P11446_0.png)
图12.LPCXpresso546xx评估板电路图(8)
![[原创] NXP LPCXpresso54628低功耗ARM MCU开发方案](/uploads/allimg/180206/162RY614_0.png)
图13.LPCXpresso546xx评估板电路图(9)
![[原创] NXP LPCXpresso54628低功耗ARM MCU开发方案](/uploads/allimg/180206/162U94064_0.png)
图14.LPCXpresso546xx评估板电路图(10)
![[原创] NXP LPCXpresso54628低功耗ARM MCU开发方案](/uploads/allimg/180206/162Z29411_0.png)
图15.LPCXpresso546xx评估板电路图(11)
![[原创] NXP LPCXpresso54628低功耗ARM MCU开发方案](/uploads/allimg/180206/16292XH7_0.png)
图16.LPCXpresso546xx评估板电路图(12)
![[原创] NXP LPCXpresso54628低功耗ARM MCU开发方案](/uploads/allimg/180206/16295X058_0.png)
图17.LPCXpresso546xx评估板电路图(13)
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