Floating-Point设计编码风格与技巧

尽管通常Fixed-Point（定点）比Floating-Point（浮点）算法的FPGA实现要更快，且面积更高效，但往往有时也需要Floating-Point来实现。这是因为Fixed-Point有限的数据动态范围，需要深入的分析来决定整个设计中间数据位宽变化的pattern，为了达到优化的QoR，并且要引入很多不同类型的Fixed-Point中间变量。而Floating-Point具有更大的数据动态范围，从而在很多算法中只需要一种数据类型的优势。

Xilinx Vivado HLS工具支持C/C++ IEEE-54标准单精度及双精度浮点数据类型，可以比较容易，快速地将C/C++ Floating-Point算法转成RTL代码。与此同时，为了达到用户期望的FPGA资源与性能, 当使用Vivado HLS directives时需要注意C/C++编码风格与技巧相结合。

编码风格

1.1 单双精度浮点数学函数

#include
float example(float var)
{
return log(var); // 双精度自然对数
}

在C设计中, 这个例子, Vviado HLS 生成的RTL实现将输入转换成双精度浮点,并基于双精度浮点计算自然对数,然后将双精度浮点输出转换成单精度浮点.

#include
float example(float var)
{
return logf(var); // 单精度自然对数
}
在C设计中, logf才是单精度自然对数, 这个例子 Vviado HLS 生成的RTL实现将基于单精度浮点计算自然对数, 而且没有输入输出单双精度的互转。

1.2 浮点运算优化

我们先来看一个例子，三个从代数上看起来差不多的写法，但其在Vivado HLS中综合出来的是三个完全不一样的结果。

void example(float *m0, float *m1, float *m2, float var)
{
*m0 = 0.2 * var; // 双精度浮点乘法，单双精度类型转换
*m1 = 0.2f * var; // 单精度浮点乘法
*m2 = var / 20.0f; // 单精度浮点除法
}

Vivado HLS将日m0, m1, m2综合成不同的RTL实现。
因为0.2是一个不能精确表征的双精度数字，所以m0运算会被Vivado HLS综合成一个双精度浮点乘法，并且将var 转换成双精度，然后将双精度乘法输出m0转换成单精度。
特别注意，如果希望Vivado HLS综合出单精度常熟，需要在常数后面加f, 如0.2f。这样m1综合成一个单精度乘法的输出。同理，m2将被Vivado HLS综合成单精度除法的输出。

我们来看另外一个例子。

void example(float *m0, float *m1, float var)
{
*m0 = 0.2f * 5.0f * var; // *m0 = var;常数乘法被优化掉
*m1 = 0.2f * var * 5.0f; // 两个双精度浮点乘法
}

再来看另一个例子。

void example(float *m0, float *m1, float var)
{
*m0 = 0.5 * var; //
*m1 = var/2; //
}
m0运算会被Vivado HLS综合成一个双精度浮点乘法，并且将var 转换成双精度，然后将双精度乘法输出m0转换成单精度。

m1运算会被Vivado HLS综合成简单的右移运算。所以如果用户希望实现对var除以2，就写成m1这种表达式，而不是m0的表达式。

并行度与资源复用
由于浮点运算相比整型，定点运算耗用更可观的资源。Vivado HLS会尽量用更有效的资源来实现浮点运算，当数据的相关性及约束许可的情况下，在Vivado HLS中，会尽量复用一些浮点运算单元。为了说明这个，我们看一个简单的四个浮点加法例子， Vivado HLS复用一个浮点加法器来串行实现四个浮点加法。
void example(float *r, float a, float b,
float c, float d)
{
*r = a + b + c + d;
}

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