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数码管
本文为大家带来四种不同的vhdl数码管动态扫描程序设计。
循环滚动,始终点亮6个数码管,左出右进。状态为:012345-123450-234501-345012-450123-501234-012345
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL
ENTITY LED2 IS
PORT(CLK:IN STD_LOGIC;
SG:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); BT:OUT STD_LOGIC_VECTOR(5 DOWNTO 0)); END LED2;
ARCHITECTURE ACE OF LED2 IS component div_2K
port(clk_in:instd_logic; clk_out:outstd_logic);
end component;
SIGNAL CNT6:INTEGER RANGE 0 TO 5;
SIGNAL A:INTEGER RANGE 0 TO 5;
SIGNAL COUNT:INTEGER RANGE 0 TO 4999 := 0;
SIGNAl FLAG:INTEGER RANGE 0 TO 6 := 0;
SIGNAl FLAG_A:INTEGER RANGE 0 TO 5;
SIGNAL clk_tmp:STD_LOGIC;
BEGIN
u1:div_2k port map(clk_in=>CLK,clk_out=>clk_tmp);
P1:process(CNT6)
BEGIN
CASE CNT6 IS --3线至6线译码器
WHEN 0 => BT <= “011111” A <= 0 --A为位码
WHEN 1 => BT<= “101111” A <= 1
WHEN 2 => BT<= “110111” A <= 2
WHEN 3 => BT<= “111011” A <= 3
WHEN 4 => BT<= “111101” A <= 4
WHEN 5 => BT<= “111110” A <= 5
WHEN OTHERS => NULL;
END CASE
END PROCESS P1;
P2:process(clk_tmp)
BEGIN
IF clk_tmp‘EVENT AND clk_tmp= ’1‘ THEN --实现模6计数器 if CNT6= 5 then CNT6<= 0; else
CNT6<=CNT6 + 1; end if;
IF (FLAG = 6) THEN --设置标志 FLAG <= 0;
END IF;
IF COUNT =4999 THEN
--相当于另一个时钟
COUNT <= 0; --计数周期为5000
FLAG <=FLAG+1; --当记满5000时左移动一位 ELSE
COUNT <=COUNT+1; --不满5000继续计数 END IF; END IF;
END PROCESS P2;
P3:process(A,FLAG,FLAG_A)
BEGIN
FLAG_A<=(( A + FLAG )mod 6) --使用求余运算实现移位
CASE FLAG_A IS --实现数码管的显示功能
WHEN 0=> SG <= “1111110”;
WHEN 1=> SG <= “0110000”;
WHEN 2=> SG <= “1101101”;
WHEN 3=> SG <= “1111001”;
WHEN 4=> SG <=“0110011”;
WHEN 5=> SG <= “1011011”;
WHEN OTHERS =>NULL
END CASE
END PROCESS P3;
END ACE;
为实现移位,关键改动为新增一个计数器,技术周期远远大于扫描周期,这样,在一个大的计数周期内,对于要显示的6位数码进行动态扫描(和实验任务1中相同),显示出6种移位状态中的一种;在下一个大的周期内,利用FLAG标志,并使用求余运算将显示位的数码移位,比如,大的计数周期为0时,FLAG为0,显示“012345”六位数码,大的周期为1时,FALG为1,此时各位求余(即FLAG_A求余)对应的数码为123450,显示的数码也就为“123450”。以此类推,实现循环移位。
本次设计选用的开发板在4位数码管输入方面只提供1个数据接口,用来动态显示4位数据,在数据输入信号方面要做到和势能控制信号同频率输出,才能保证数码显示不会出错或显示移位。该模块部分VHDL源程序如下:
在EDA/SOPC装置中,图示数码管显示采用的是动态扫描方式,即当扫描选通电路74LS138输入为000,(SEL2、SEL1、SEL0为000时,)Y0输出低电平,8个数码管中左边第一个数码管被选通,此时,应在数码管输入端输入相应数据。其中,74LS245起输出驱动作用。
人眼视觉暂留频率在24Hz以上,如果大于该频率,点亮单个七段显示器,看上去能有8个同时显示的效果,而且显示也不闪烁。因此,选通频率要大于24Hz以上。 依据实验装置电路,完成七段LED显示译码器的设计应包含如下电路:
①分频电路:将10MHz脉冲分频到1kHz;
②七段译码电路;
③扫描计数电路:完成模8的计数电路,为扫描选通做准备;
④扫描选通电路:利用分时传输思想,将要显示的数据依次传入数码管显示电路。
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
ENTITY xianshi IS
PORT(clk:in std_logic;
smg:out std_logic_vector(7 downto 0);
sel:out std_logic_vector(2 downto 0));
END ENTITY;
ARCHITECTURE func OF xianshi IS
SIGNAL fp,tmp:std_logic;
SIGNAL count:std_logic_vector(9 downto 0);
SIGNAL sl:std_logic_vector(2 downto 0);
BEGIN
PROCESS(clk)
BEGIN
IF(clk‘EVENT AND clk = ’1‘)
THEN IF(count = “1111100111”)
THEN count <= (OTHERS => ’0‘);
tmp <= NOT tmp; ELSE
count <= count + 1; END IF;
END IF; fp <= tmp;
END PROCESS;
PROCESS(fp)
BEGIN
IF(fp’EVENT AND fp = ‘1’)
THEN IF(sl = “111”)
THEN sl <= “000”;
ELSE
sl <= sl + 1; END IF;
END IF;
END PROCESS;
sel <= sl;
PROCESS(sl) BEGIN
CASE sl IS
WHEN “000” => smg <= “01000000”;
WHEN “001” => smg <= “01111001”;
WHEN “010” => smg <= “00100100”;
WHEN “011” => smg <= “00110000”;
WHEN “100” => smg <= “00011001”;
WHEN “101” => smg <= “00010010”;
WHEN “110” => smg <= “00000010”;
WHEN “111” => smg <= “01111000”;
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END ARCHITECTURE;
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