atmega64 pdf

The ATmega64 provides the following features: 64K by tes of In-System Prog rammable
Flash with Re ad-While-Write capabilities, 2K bytes EEP ROM, 4K bytes SRAM, 53 gen-
eral purpose I/O lines, 32 general purpose w orking registe rs, Real Time Counter (RTC),
four flexible Timer/Counters with compare modes and PWM, two USARTs, a byte ori-
ented Two-wire Serial Interface, an 8-channel, 10-bit ADCwith optional differential input
stage with programmable g ain, programmable Watchdog Timer with internal Oscillator,
an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for
accessing the On-chip Debug system and programming, and six software selectable
power saving modes. The Idle mode stops the CPUwhile allowing the SRAM,
Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-
down mode saves the register contents but freezes the Oscillator, disabling all other
chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asyn-
chronous timer continues to run, allowing the user to maintain a timer base while the
rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all
I/O modules except asynchronous timer and ADC, to minimize switching noise during
ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the
rest of the device is sleeping. This allows very fast start-up combined with low power
consumption. In Extended Standby mode, both the main Oscillator and the asynchro-
nous timer continue to run.