36兆位QDR®II SRAM两词突发结构cy7c1412kv18

　　The CY7C1425KV18， CY7C1412KV18， and CY7C1414KV18 are 1.8 V synchronouspipelined SRAMs， equipped with QDR II architecture. QDR II architecture consists of two separate ports： the readport and the write port toaccess the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input （K） clock. Accesses to the QDR II read and write ports are completely independent of one another. Tomaximize data throughput， both read and write ports are equipped withDDRinterfaces. Each address location is associated with two 9-bit words （CY7C1425KV18）， 18-bit words （CY7C1412KV18）， or 36-bit words （CY7C1414KV18） that burst sequentially into or out of the device. Because datacanbe transferred into and out of the device on every rising edge of both input clocks （K and K and C and C）， memory bandwidth is maximized whilesimplifying system design by eliminating bus turnarounds. Depth expansion is accomplished with port selects， which enables each port to operate independently. All synchronous inputs pass through input registers controlledby the K or K input clocks. All data outputs pass through output registers controlled by the C or C （or K or K in a single clock domain） input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. For a complete list of related documentation， click here.