cy7c1347g 4兆位（128K的×36）流水线同步SRAM

　　The CY7C1347G is a 3.3 V， 128K × 36 synchronouspipelined SRAMdesigned to support zero-wait-statesecondary cache with minimal gluelogic. CY7C1347G I/O pinscanoperate at either the 2.5 V or the 3.3 V level. The I/O pins are 3.3 V tolerant when VDDQ = 2.5 V. All synchronous inputs pass through input registerscontrolledby the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock.Maximum access delay from the clock rise is 2.6 ns （250 MHz device）。 CY7C1347G supports either the interleaved burst sequence used by theIntelPentium processor or alinearburst sequence used by processors such as the PowerPC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either theaddress strobe from processor （ADSP） or the address strobe from controller （ADSC） at clock rise. Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the four Byte Write Select （BW［A:D］） inputs. A global write enable （GW） overrides all byte write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self timed write circuitry. Three synchronous chip Selects （CE1， CE2， CE3） and an asynchronous output enable （OE） provide for easy bank selection and output tristate control. To provide proper data during depth expansion， OE is masked during the first clock of a read cycle when emerging from a deselected state. For a complete list of related documentation， click here.